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| A Core Union Test Scheme for Reducing System on Chip Test Time |
| YI Maoxianga,LIANG Huaguoa,WANG Weib,ZHANG Leib |
| (a. School of Electronic Science and Applied Physics; b. School of Computer and Information, Hefei University of Technology, Hefei 230009, China) |
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Abstract An extended pattern runlength (xPRL) coding approach was introduced, which uses a dynamic don’t care bit propagation strategy to improve test data compression. Multiple core test sets for testing system on chip (SoC) are merged into a single data stream and compressed by the xPRL coding. A reconfigurable serial scan chain was designed to make the test vectors of different cores unionapplicable. The proposed scheme was applied to an example of SoC with six large ISCAS’89 benchmarks embedded. The analysis and experimental results show that compared to the previous techniques, in which a test set is compressed and applied independently of others, our technique can increase compression rate and, at the same time, reduce redundant shift and capture cycles during scan testing, which thereby can effectively reduce test application time of SoCs.
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Received: 17 February 2009
Published: 26 February 2010
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