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| TR-TC Associated Test Cost Mathematical Model in SoC Using Controllable Multi-Scan-Enable |
| ZHANG Jin-Yi-a, b , c , HUANG Xu-Hui-b, CAI Wan-Lin-b, WENG Han-Yi-a, c |
| (a. Key Laboratory of Special Fiber Optics and Optical Access Networks (Shanghai University), Ministry of Education； b.Microelectronic Research & Development Center； c.Key Laboratory of Advanced Displays and System Application, Ministry of Education, Shanghai University， Shanghai 200072， China) |
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Abstract Based on the scan chain structure of SoC（System-on-Chip）, this paper described a method of multi-Scan-Enable DFT for at-speed testing to improve the transition fault coverage. A TR-TC (Test Resources-Test Coverage) associated test cost mathematical model was built. The results show that the TR-TC model can effectively control the complexity of at-speed DFT and establish the optimization number of Scan-Enable, which provides a reliable target control value in multi-Scan-Enable at-speed DFT.
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Received: 19 July 2010
Published: 29 July 2011
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