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| Design of System Level Simulation Platform for Dynamic Reconfigurable Many-Core Processor |
| HAN Xing, JIANG Jiang, FU Yu-Zhuo, ZHOU Chuan, LIU Zi-Yang, YANG Kai-Kai |
| (School of Microelectronics, Shanghai Jiaotong University, Shanghai 200240, China) |
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Abstract A dynamic reconfiguration technique based on the partitioning of computing resources on many-core processor was introduced. According to the locality principle, both the hardware support, including dynamically reconfigurable sub-netting in NoC and dynamically reconfigurable Cache coherence protocol, and the scheduling algorithm for on-chip computing resources are designed to improve the utilization of the many-core processor. This paper also introduced the simulation platform for dynamically reconfigurable many-core processor, which is developed based on system level simulator Gem 5. The Cache coherence protocol with sub-netting and scheduling algorithm mentioned above was implemented. The simulation result proves the improvement for performance of the manycore processor.
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Received: 30 May 2012
Published: 30 January 2013
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