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Abstract To maximize the utilization of the bottleneck workstation, and achieve a high throughput as well as a reasonable cycle time, a heuristic algorithm was put forward for determining the right time buffer before the bottleneck workstation in semiconductor wafer fabrication system. Firstly, a G/G/m queuing model is proposed based on the queuing theory and the system’s random variability. Secondly, according to the characteristics of reentrance of the bottleneck workstation, a time buffer decomposition method is presented. On the basis of the work mentioned above, a heuristic algorithm is built for determining the reasonable time buffer. Finally, a release policy is proposed based on the time buffer, and a simulation experiment is designed to evaluate the proposed algorithm. The results indicate that the algorithm is valid and feasible.
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Received: 14 November 2011
Published: 29 December 2012
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