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| A Novel Networks-on-Chip Topology for Three Dimensional Microprocessor |
| WANG Di-1, BAI Han-2, ZHAO Tian-Lei-1, TANG Yu-Xing-1, DOU Qiang-1 |
| (1. College of Computer, National University of Defense Technology, Changsha 410073, China;2. Jiangsu Unit, Chinese People’s Armed Police Force, Nanjing 210036, China) |
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Abstract By utilizing silicon via’s characteristics such as short delays and less power consumption, this paper designed a new kind of topology 3DE-Mesh for a three dimensional networks-on-chip which has more than 10 layers of stacked dies. By analyzing the experimental data the paper proves 3DE-Mesh’s function and scalability. The simulation results indicate that the 3DE-Mesh satisfies the requirements of the three dimensional integrated circuits which has more than 10 layers of stacked dies.
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Received: 30 May 2012
Published: 30 January 2013
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