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| Design of a 2 GHz L2 Cache for 16-core Processor |
| LI Yong-Jin, DENG Rang-Yu, YAN Xiao-Bo, YI Xiao-Fei, ZHOU Hong-Wei, ZHANG Ying |
| （College of Computer, National University of Defense Technology, Changsha 410073, China） |
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Abstract An L2 Cache design scheme was provided to process the memory access with high efficiency. L2 Cache manages data coherency with L1 Cache by the improved directory protocol, and manages date coherence with other L2 Caches and L3 Caches by cooperating with directory control unit. An MESIAF Cache coherency protocol was implemented. The stage of pipeline is small, so load data can be returned to core in advance. The potential deadlock was resolved by two dependence list. The leakage power is decreased by sleeping the data array and just waking up them before used. The dynamic power is decreased by applying the fine gate clock. The result of backend design shows that the design frequency reaches 2 GHz. The design has been used in a 16-core processor chip successfully.
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Received: 30 July 2012
Published: 30 January 2013
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