INTRODUCTION
The human brain, a highly interconnected complex network structure constructed by enormous quantity of neurons and synapses, is one of the most powerful biological information-processing organs on the earth. In such a complex network, neurons work as the receptors and processors of information, and synapses are the carriers for the pattern of information exchanged between neurons. This network structure not only endows the human brain with excellent logical reasoning, abstract thinking, and creativity1 but also suppresses the power consumption down to 20 W even when performing high-complexity multi-information parallel processing2. In recent years, the field of neural networks, which simulates the structure of neurons and synaptic connections in the human brain, has undergone tremendous progress and transformation. On the one hand, the computational capabilities of silicon-based chips still continue to rise3, albeit the growth rate predicted by “Moore's Law” is slowed down. On the other hand, the sustained innovation of deep-learning theories and architectures4 offer more and more opportunities for the widespread application of neural networks in various fields, including but not limited to pattern recognition5, computer vision6-8, natural language processing9-11, etc. Particularly, OpenAI's ChatGPT12 and Sora13 have led technological innovations in the fields of natural language generation and video content generation, respectively. However, this rapid progress is also accompanied by a fast increasing demand for computational resources and energy14,15. Therefore, how to balance the performance of neural networks and the requirement of computational resources and energy has become a major challenge. Unlike the continuous signals in traditional deep learning, spike neural networks (SNNs) adopt pulse signals as a form of data transmission. Instead of transmitting each discrete pulse in real time, the neurons decide whether to pass the pulse signal to other neurons based on the cumulative effect of multiple pulse signals, a mechanism known as the event-triggered mode. Such a mode renders SNNs for high efficiency and low energy consumption characteristics, which has been confirmed in various fields16-19.
The hardware implementation of SNNs is key to further reducing their energy consumption. SNNs have achieved substantial success at the aspect of software, however, there still remain tremendous challenges in hardware implementation. Nowadays, many matured neural network hardware based on traditional complementary metal-oxide semiconductor (CMOS) devices have been developed including central processing units (CPUs)20, graphics processing units (GPUs)21, field-programmable gate arrays (FPGAs)22, application-specific integrated circuits (ASICs)23, etc. CPUs exhibit fast computing performance but poor parallel processing capabilities, and the power required by GPUs is too large to be deployed at the terminal. Therefore, some alternative technologies have been developed for acceleration, for example, flexible and reprogrammable low-power field-effect transistor arrays (FPGAs), or highly optimized and application-specific custom accelerators. These accelerators usually appear in the form of ASICs, which provide greater design flexibility and higher energy efficiency, especially for the inference process in artificial intelligence. Large-scale SNN hardware based on FPGAs24,25 and ASICs (such as TrueNorth26) has also been realized and remarkable achievements have been made. However, limited to their von Neumann architecture, the advantage of SNNs in energy consumption has not been fully exploited yet. In contrast, emerging technologies that are compatible with the “in-memory computing” such as phase-change memory, resistive memory (RRAM), magnetic memory, and ferroelectric memory have shown better potential in the hardware implementation of SNNs. Among them, RRAM (i.e., memristors) has become a strong candidate for simulating the key units (neurons and synapses) of SNNs due to the merits of scaling potential (>10 nm)27, fast switching speed (sub-nanosecond)28, low programming current (nanoampere)29 and high durability (<1012)30. The exciting aspect of a two-terminal memristor array as network synapses is that, the computation and storage of data are physically separated in modern computers based on the von Neumann architecture, leading to the need for data to be transmitted back and forth between the computing unit and the storage unit31. This inevitably introduces issues of latency and energy consumption32. Particularly for neural networks that require memory-intensive computing, bandwidth limitations and energy consumption are the main challenges33. In contrast, in the human brain, the computation and storage of data can occur in the same physical space. This new computing architecture is referred to as “in-memory computing”34. The memristor arrays used for SNN hardware can meet the requirements of “in-memory computing” through the physical laws of Ohm's law and Kirchhoff's law35, which reduces latency and energy consumption.
Although there already have been many reviews on memristors in terms of neural networks, covering the aspects of synaptic function implementation, integrated network training and operation, as well as neuromorphic computing applications36-39. However, memristors have some inherent non-ideal characteristics, such as a limited number of conductance states, non-linear regulation, and randomness among others. The optimization of algorithms/architectures based on these inherent characteristics has not yet been fully explored, especially in the area of memristor-based hardware implementation of SNNs. Therefore, this paper starts from the basic principles of SNNs, then introduces the memristor-based technologies for hardware implementation of SNNs, and subsequently discusses the challenges of hard implementation from both the algorithmic and hardware perspectives. Finally, we focus on the algorithm optimization for memristors so as to provide a reference for the implementation of high-performance SNNs based on memristors. Based on the existing memristor technology, the current problems and challenges in this field are also summarized.
SPIKING NEURAL NETWORKS
Neural networks can be classified into three generations by Maass40. The first generation, for instance, are perceptrons, which generate a singular numerical output through the execution of threshold operations41. Based on this, the second generation introduced continuous non-linear functions, such as the sigmoid function, rendering the output being continuous42. This evolution, supported by the noted backpropagation (BP), is culminated in today's deep neural networks (DNNs)43. The principal distinction between the third generation and its predecessors lies in the mode of information transmission, where pulse signals replace real values44. In terms of composition, SNNs are similar to traditional artificial neural networks (ANNs), in which neurons are interconnected to build specific structures via synapses. In the aspect of information transmission, however, SNNs operate in a completely different way. Specifically, in traditional ANNs, signals from the preceding layer are multiplied by corresponding synaptic weights and then summed, prior to being conveyed to neuron. After that, the neuron processes this signal through an activation function and transmits it to the next layer. In SNNs, pulse signals also need to be multiplied by synaptic weights and summed before being transmitted to neuron, but the result is not directly conveyed to the activation function. Instead, the neuron accumulates the effects of these signals over time till reaching a threshold. Afterwards, a pulse is emitted to the next layer, as depicted in Fig. 1a44-47. This implies that, unlike traditional neural networks, SNNs do not need to activate all the synaptic weights and neurons for computation at each time step. Instead, they rely on the cumulative effect of multiple pulse signals to determine whether to continue transmitting the signal, which significantly reduces the energy consumption and enhances the efficiency.
Fig. 1. Schematic of SNNs model. a, Classical SNNs structure, comprising a post-neuron driven by input pre-neurons. Reprinted with permission from ref.44. © 2019 Nature Publishing Group. b, SNNs flow chart. c, The dynamics of LIF spiking neurons is shown. d, The spike-timing-dependent plasticity (STDP) Rule. Abbreviations: LIF, Leaky Integrate-and-Fire; SNNs, spike neural networks. |
Neuron
A multitude of spiking neuron models have been proposed, depending on various degrees of biomimicry, for instance, the highly biomimetic Hodgkin-Huxley (HH) model, which meticulously delineates the variations in voltage and current on the neuronal cell membrane. In this model, the passive electrical properties of the neuronal cell membrane, and the dependence of sodium-channel and potassium-channel conductance on membrane potential and time, are taken into account48. Despite matching well with the electrophysiological experimental results of biological neurons, the high computational cost of HH model makes it unsuitable for large-scale networks49. The Izhikevich model simplifies the HH model. This model takes into account of the membrane potential of the neuron and a recovery variable. This recovery variable represents the activation effect of the potassium-ion current and the inactivation effect of the sodium ion, thus providing negative feedback to the membrane potential50. Therefore, the Izhikevich model operates in a low computational complexity but still retains various firing modes of biological neurons, such as periodic discharge, burst discharge, etc. Although these bionic neuron models perform well, it is worth noting that not all applications require such a high-level but excessive power consumption biomimicry. It is necessary to balance the degree of biomimicry and computational cost according to the needs of specific applications. Therefore, the commonly adopted SNN neuron model is the Leaky Integrate-and-Fire (LIF) neuron model51, which simulates the basic dynamic behavior of neurons in a concise and efficient manner: the membrane potential of the neuron changes with the input current. Once the membrane potential reaches a certain threshold, the neuron will generate a pulse, and then the membrane potential will fall back to the resting value. The LIF model has succeeded in neural network researches45,52, 53, 54, 55. The excellent balance achieved between perfect imitation and energy efficiency makes it more suitable for large-scale neural network applications. The basic membrane potential dynamics of this model can be described by the following formula:
$I_{\mathrm{in}}(t) R_{\mathrm{m}}=U_{\mathrm{mem}}(t)+\tau_{\mathrm{m}} \frac{d U_{\mathrm{mem}}(t)}{d t}$
$U_{\mathrm{mem}}(t)=I_{\mathrm{in}}(t) R_{\mathrm{m}}+\left[U_{0}-I_{\mathrm{in}}(t) R_{\mathrm{m}}\right] e^{-\frac{t}{\tau_{\mathrm{m}}}}$
Where, Iin(t) denotes the current input value, Rm is the membrane resistance, Umem(t) represents the membrane potential, τm is the membrane time constant, t is the time, and U0 is the initial membrane potential. The Umem(t) accumulates the effect of signals according to the aforementioned formula until it reaches a threshold, then fires a pulse and resets the Umem(t) to the resting state (red line in Fig. 1b). It is also worth noting that the Umem(t) decays in the form of β(e−t/τm) (blue line in Fig. 1b) all the time. Therefore, the effect of aforementioned accumulation depends on the intervals of the signals. The dynamics of a single LIF neuron is depicted in Fig. 1c. In addition, there is a simplified model similar to LIF, namely the Integrate-and-Fire (IF) neuron model. In this model, the decay function in the Umem(t) with time has been removed, resulting in a constant Umem(t) even if no signal is received. Building upon the LIF model, in addition to its simplification to the IF model, there are more complex spike response model (SRM) neurons. After firing a pulse, these neurons enter a brief refractory period, during which they do not respond to any input. Moreover, in a neural network composed of SRM neurons, the activation of one neuron will briefly inhibit the activation of its neighboring neurons, which is a phenomenon known as lateral inhibition. Typically, the refractory period lasts longer than the duration of lateral inhibition, ensuring that the neuron has sufficient recovery time after firing a pulse. SRM neurons can simulate the adaptive behavior of biological neurons to continuous stimuli, avoid information overload through the refractory period, and support competitive learning through lateral inhibition. SRM neurons with refractory periods and lateral inhibition are of significant importance for unsupervised local training methods, such as spike-timing-dependent plasticity (STDP), which enables neurons to have higher adaptability and flexibility when dealing with complex tasks56. In addition, there are adaptive threshold neurons that can dynamically adjust the threshold according to the input data, such as the Double Exponential Adaptive Threshold neuron. The use of this neuron can improve the convergence speed and accuracy of the network, and it can enhance the memory capacity of the network by taking both long-term and short-term input information into consideration. Moreover, researches have shown that networks that use adaptive threshold neurons have strong resistance to minor hardware changes, which demonstrates good robustness57.
Synapse
For synapses, their “weight” plasticity is the foundation of biological learning and memory functions58. The essence of neural network training is to adjust the synaptic weights through some kinds of method59. In SNNs, the pulse signal is discrete, and the activation function is non-differentiable, so the BP algorithm cannot be directly used as in ANNs to accurately update synaptic weights. As for the training methods of SNNs, they can be roughly divided into two types: rule-based and optimization-based.
Rule-based learning methods are inspired by STDP and reward-modulated STDP (R-STDP) in biology. The basic principle of the STDP rule is that the strength of the synaptic connection between the pre-neuron and the post-neuron will be strengthened or attenuated depending on the order in which they are activated. In this way, STDP can realize the self-organization and functional differentiation of neurons, that is, unsupervised learning functions, as shown in Fig. 1d60,61. Similarly, R-STDP adopts STDP to regulate synaptic plasticity, but the training is under the guidance of external reward signals. Upon this, the goal orientation and behavior selection of neurons can be achieved, namely, weakly supervised learning functions62,63. These two rule-based learning algorithms exhibit the characteristics of high efficiency and adaptability. Peter U. Diehl et al. used the STDP rule to train SNNs and achieved 95% accuracy in the Modified National Institute of Standards and Technology database (MNIST) benchmark test. The network structure they built contains two layers (as shown in Fig. 2a): the input layer and the processing layer. The processing layer is composed of excitatory and inhibitory neurons. The latter ones are employed to achieve lateral inhibition, and at the same time, an adaptive threshold is introduced in the neurons to prevent a single neuron from dominating the response mode and thus ensure the differentiation of the receptive field of the neurons64. However, these methods ignore the complex dynamic process and task information inside the network when designing, and as a result, the prediction accuracy tend to decline quickly with increasing number of layers.
Fig. 2. Training of synaptic weights. a, Unsupervised STDP network structure. Reprinted with permission from ref.64. © 2015 Diehl and Cook. b, Schematic diagram of the structure of the BP algorithm based on STDP. Reprinted with permission from ref.65. © 2019 Elsevier B.V. c, Modification of the CNN structure according to the requirement of SNNs, before (left) and after (right). Reprinted with permission from ref.46. © 2014 Springer Science+Business Media New York. Abbreviations: BP, backpropagation; CNN, convolutional neural network; STDP, spike-timing-dependent plasticity. |
Optimization-based methods minimize the error between the output and the expectation through mathematical means, introducing BP to optimize the network globally during the training process. Amirhossein Tavanaei et al. proposed a BP algorithm based on STDP, as shown in Fig. 2b. The core idea is to use the approximate relationship between Rectified Linear Units neurons and IF neurons to transform the traditional BP update rule into an STDP rule based on pulse time. This method retains the accuracy of BP while utilizing the biological rationality and computational efficiency of STDP65. A threshold-dependent batch normalization method based on STDP backpropagation has also been proposed, achieving direct training of high-performance deep SNNs on ImageNet and efficiently implementing its inference on neuromorphic hardware66. However, introducing rule-based local training methods (such as STDP) during training preserves biological rationality but can lead to lower accuracy, limiting the competitiveness and practical application of SNNs. BP based entirely on gradient descent is more likely to achieve high-precision training of models67-69. Backpropagation through time (BPTT) has become an efficient supervised learning algorithm for training SNNs, with BPTT divided into forward propagation, BP, and weight update. Because the neurons of SNNs are dynamic, BP needs to be performed over the entire time step, propagating from the last time step to the first, the opposite of forward propagation. During BP, it is necessary to calculate the pulse gradient and neuron membrane potential gradient at each time step, using these gradients to update the weights of the SNN model to reduce loss. The current mainstream accelerators are still used for ANN series networks, but accelerators based on BPTT training SNNs are also being actively explored for training SNNs70.
In addition to directly training SNNs, there is another solution based on converting ANNs to SNNs (ANN2SNN). For example, Yongqiang Cao et al. proposed a method to convert convolutional neural networks (CNNs) to SNNs, in which the corresponding CNN structure has been modified according to the requirements of SNNs before training, such as eliminating negative inputs and biases, adopting HalfRect activation functions, and using linear subsampling; detailed information are shown in Fig. 2c. After training the structured CNN by BP algorithm, the trained CNN weights are mapped to a similar SNN architecture46. In this way, the merits of the low-power-consumption and high-efficiency advantages of SNNs can be acquired at the cost of almost no loss to the accuracy of the ANN counterpart71. However, most of the ANN2SNN methods are based on frequency coding, which means that a long time step to accumulate the output pulses of neurons is required to get accurate results. This will undoubtedly increase the inference time and power consumption of SNNs and thus reduce their efficiency. In other words, this method is not suitable for online learning72. Online learning is capable of updating model parameters to adapt to the changes in data distribution in real time, which requires SNNs to have capabilities of continuous learning.
In the current field of machine learning, mainstream platforms such as TensorFlow, PyTorch, and Keras do not provide sufficient support for SNNs. Therefore, to build, train, and deploy SNNs more efficiently, frameworks specifically designed for SNNs are needed. In this regard, many researchers have conducted in-depth exploration. For example, SpikingJelly is a framework developed for the construction, training, and deployment of spike-based intelligent systems73. It provides efficient simulation and acceleration methods for SNNs and is based on the PyTorch framework; thus, it can utilize the parallel computing capabilities of GPUs. SpikingJelly supports various spiking neuron and synapse models, and researchers can choose the appropriate model according to their needs. In addition, SpikingJelly also provides a fast ANN-SNN conversion interface, preprocessing of neuromorphic datasets, and SNN analysis functions. There is also Snntorch, which is also based on the PyTorch framework. It is a framework specifically used for gradient optimization of spiking neural networks74. It provides pre-designed spiking neuron models and is deeply integrated with PyTorch, allowing researchers to develop and train SNNs in a familiar environment. The downside is that compared to some static graph frameworks (such as TensorFlow), the training speed of Snntorch is slower. There is also Brian2, an upgraded version of Brian, developed based on the Python programming language75. Brian2 is an equation-oriented simulator that allows researchers to directly define neuron and synapse models using mathematical equations, providing greater flexibility in building neural networks. Brian2 can also automatically convert user-defined models into efficient low-level code, which is very useful for simulating large-scale networks. All of the aforementioned frameworks provide researchers with more efficient ways to build, train, and deploy SNNs, laying a solid foundation for the future development of SNNs.
MEMRISTOR
Since the memristor theory proposed by Chua was linked to the resistive switching phenomenon of TiO2 devices by HP Labs in 200876, this field has been widely explored. In addition to various binary oxide-based materials77, 78, 79, 80, 81, there are also chalcogenides82,83, two-dimensional materials84,85, organic materials86,87, etc., that have been reported in the researches of memristors, and a relatively matured theory on memristors has been developed88. A typical memristor is usually a two-terminal configural resistor device (metal-insulator-metal), with a memory function of non-linear response characteristics. It is the fourth type of circuit element in addition to resistance, capacitance, and inductance, with the advantages of high speed, low power consumption, and high scalability89. Especially, they have important application prospects in the fields of information storage, logic operations, neural networks, etc.90. Memristors have different physical mechanisms according to the selection of the dielectric layer and electrodes, which would not be discussed in detail here. Generally, it is widely accepted that under the action of an electric field, the migration of electrons and ions or some other physical particles work together to induce local structural changes in the material, which in turn leads to changes in the conductive state91. According to the different ability of maintaining conductivity, memristors can be divided into two categories: non-volatile and volatile.
Non-volatile
Taking the most classic resistive switching mechanism (ionic effect) as an example, it can be divided into valence change memory92 and electrochemical metallization memory93, which correspond to the mechanism of oxygen anions (dielectric layer) and active metal ions (electrodes) directed moving under an electric field to eventually form conductive filaments (CFs), respectively, as shown in Fig. 3a. The fundamental I-V curve is depicted, as in Fig. 3b. In the off state, as the positive voltage increases, the conductance changes from a high-resistance state (HRS) to a low-resistance state (LRS); in the on state, as the negative voltage decreases, the conductance changes back from a LRS to a HRS, and the read voltage always remains at a low positive voltage94. However, this ion-conduction-based method will bring some problems, for example, continuous write-erase operations will cause durability failures due to the destructive nature of the programming method, and the conductance state after programming will drift over time. Therefore, even if the on/off ratio of device is very large, there are only a few stable and available conductance states that can be reached. Non-volatile memristors are mainly used to simulate synaptic plasticity by adjusting their multi-level conductance states in neural networks37,95,96. which puts higher requirements on the linearity, symmetry, durability, and retention of the memristor working curve. To meet these requirements, researchers are keep optimizing relevant performance through doping, interlayering, annealing, and other methods. Interlayering can effectively improve the linearity and symmetry of memristor conductance curves. Zongwei Wang et al. inserted a SiO2 layer that restricts oxygen-ion diffusion at the TiN/TaOx interface (Scanning Transmission Electron Microscopy (STEM) image is shown in Fig. 4a) to achieve uniform conductance modulation. This method can effectively suppress the growth/dissolution rate of CFs in memristors, thereby achieving more uniform conductance modulation, increasing linearity and symmetry (Fig. 4b-c)97. Lei Wu et al. found that the resistance evolution of Al-doped HfO2 devices is milder than that of undoped Al (Fig. 4d) and that multi-value storage of devices can be achieved by changing the limiting current or using pulse sequences and that the retention time of the multi-conductance state of the device exceeds 104 s at 85 °C98. Woo Sik Choi et al. inserted Al2O3 into InGaZnO memristors, achieving higher durability and more stable transient characteristics. As shown in Fig. 4e, in 500 scanning cycles, compared with the instability of the S1 (without Al2O3 intercalation) conductance state, the conductance fluctuation of S2 (with Al2O3 intercalation) is much smaller. Moreover, the high resistance of Al2O3 can suppress thermal fluctuations, and S2 shows more stable transient characteristics and smaller resistance state changes (Fig. 4f)99. Interlayering combined with doping can further improve the durability and retention of memristor conductance. Yun-Lai Zhu et al. used the method of interface doping (combination of doping and interlayering) to improve the performance of TiN/HfO2/Pt memristors. They prepared two optimized devices with different insertion configurations, namely TiN/HfO2/HfO2:Al/Pt and TiN/HfO2:Al/HfO2/Pt. The former device showed improved durability and retention, whereas the latter showed a decline in performance. This is because different insertion positions lead to different CF formation/breakdown mechanisms; therefore, it is necessary to pay attention to the impact on CF formation/breakdown in the meantime101. Annealing treatment in inert atmosphere can improve the uniformity of ion or vacancy distribution in the device, further optimizing and stabilizing the performance of memristors. Yongyue Xiao et al. studied the effect of N2 environment annealing treatment on the performance of Pt/HfO2/BiFeO3/HfO2/TiN structure memristors. After N2 annealing, the uniformity of the memristor (Fig. 4g), and the pulse linearity were improved (Fig. 4i). Furthermore, the durability was increased by 103 times (Fig. 4h). As we know, the conductance regulation of oxide-type memristors can be attributed to the migration of oxygen vacancies to form CF. Annealing in N2 produces more oxygen vacancies in the oxide, therefore, resulting in a better control to the conductance of memristors100.
Fig. 3. Basic performance diagram of a non-volatile memristor. a, The principle of two different conductive filaments. b, Fundamental I–V curve of non-volatile memristors. Reprinted with permission from ref.94. © 2023 The Author(s). |
Fig. 4. Performance optimization for non-volatile memristors. a, STEM image of a TiN/SiO2/TaOx/Pt device. Comparison of conductance curves for no intercalation (b), and intercalation (c). Reprinted with permission from ref.97. © 2016 Royal Society of Chemistry. d, Al-doped and non-doped I–V curves. Reprinted with permission from ref.98. © 2019 The Author(s). e, Measured endurance and f, transient characteristics with or without intercalation. Reprinted with permission from ref.99. © 2022 Elsevier Ltd. g, The cumulative probability distribution of set and reset voltage of both devices (N2 annealing is red). h, Endurance test (N2 annealing is red). i, The reproducible conductance modulation of N2 annealing device under amplitude-repeated potentiation and depression pulses. Reprinted with permission from ref.100. © 2022 Elsevier Ltd and Techna Group S.r.l. Abbreviation: STEM, Scanning Transmission Electron Microscopy. |
In neural networks, non-volatile memristor cross arrays are adopted to simulate synaptic network structures. These cross arrays can not only store weight parameters but also provide computational capabilities (storage and computation in one), physically implementing the main workload of network computation—vector matrix multiplication (VMM) based on Ohm's law and Kirchhoff's current law (this is consistent in ANN and SNN). J. Joshua Yang and Qiangfei Xia et al. employed hafnium dioxide memristors to build a reconfigurable cross array (128 × 64), as shown in the left figure of Fig. 5a, and the right figure of Fig. 5a shows the chips integrated with different-scale memristor arrays and related testing equipment as well as the microscope images of four 1T1R. This cross array exhibits a high yield (99.8%), high stability (no drift after 6.4 h), multiple conductance states (6 bits), and a good linear I-V relationship102. They adopted this cross array to demonstrate signal processing, image compression, and convolutional filtering103, moreover, further evaluation on the computational accuracy of the VMM produced by this array was performed, which can reach a classification accuracy of 89.9% on the MNIST handwritten digit set104. The network trained in situ with this cross array even showed competitive classification accuracy on standard datasets105. In order to increase the array scale to achieve more complex tasks, Qi Liu et al. proposed a fully integrated memristor-based computing-in-memory (CIM) chip, the array scale could reach 158.8 kb. This chip innovatively adopted a sign-weighted 2T2R (SW-2T2R) structure to reduce the accumulated source line current (ISL), which significantly reduces the adverse effects brought by IR drop. And the chip also exhibits a low-power interface design, that is, achieving a flexible trade-off between system accuracy and power consumption by employing a resolution-adjustable LPAR-ADC, and the layout structure of SW-2T2R and LPAR-ADC is depicted in Fig. 5b. Then they employed this chip to implement a fully integrated multilayer perceptron (MLP) (784-100-10) model, and high-recognition accuracy (94.4%), high-inference speed (77 μs/image), and 78.4 TOPS/W peak energy efficiency were achieved on the MNIST database by this model, showing the significant advantages of the CIM chip based on large-scale memristor arrays106. More complex CNN memristor hardware was also implemented in the same year. Huaqiang Wu et al. adopted eight memristor arrays (each 2048 units) to successfully build a five-layer CNN hardware; the integrated printed circuit board (PCB) subsystem is shown in Fig. 5c, where the processing element (PE) chip has 2048 memristors and on-chip decoder circuits. This hardware uses a hybrid training method to adapt to device defects and parallel convolution technology so as to eliminate the throughput gap between memristor-based convolution computation and fully connected (FC) VMM. On the MNIST dataset, the image recognition accuracy was further improved to 96%, and its energy efficiency was two orders of magnitude higher than that with Nvidia Tesla V100 GPU107,109.
Fig. 5. Non-volatile memristor arrays. a, A photo of a probe card touching a 128 × 64 1T1R array. A photo (2 cm × 2 cm) showing two 1T1R memristor crossbars dies with various array sizes and test devices. A photomicrograph of four cells in a 1T1R array (10-μm scale bar) and its structure (from left to right). Reprinted with permission from ref.103. © 2017 Macmillan Publishers Limited, part of Springer Nature. b, A photomicrograph of a CIM chip based on a memristor array (158.8 kb), which includes the layout of SW-2T2R units and resolution-adjustable LPAR-ADC units. Reprinted with permission from ref.106. © 2020 IEEE. c, A photograph of an integrated PCB subsystem, including an image of a partial PE chip with a 2048 memristor and on-chip decoder circuits. Below is a schematic of the 1T1R connections on the PE chip. Reprinted with permission from ref.107. © 2020 The Author(s), under exclusive licence to Springer Nature Limited. d, SEM images of the 1-kb crossbar arrays (CAs) Reprinted with permission from ref.108. © 2024 The Author(s). Abbreviations: CIM, computing-in-memory; PCB, printed circuit board; PE, processing element; SEM, scanning electron microscopy. |
It is worthy to be noted that the aforementioned memristor arrays all adopt a 1T1R structure, which is similar to that of dynamic random-access memory. Its operation principle and usage are quite intuitive, and it can effectively isolate the mutual influence of currents between different units. However, the inclusion of transistors increases the complexity and limits the scalability of the system. Therefore, transistor-less metal oxide memristor crossbar arrays (0T1R) have also been actively explored. M. Prezioso et al. have realized a transistor-less crossbar array based on Al2O3-/TiO2-x-stacked metal oxide memristors for the first time and adopted this array to implement a simple integrated neural network (single-layer perceptron). They demonstrated in-situ training with the adoption of a coarse-grained delta-rule algorithm and performed pattern recognition on 3 × 3 pixel black and white images36. F. Merrikh Bayat et al. also demonstrated a fully integrated three-layer neural network hardware based on the mixed signals. This hardware consists of two 20 × 20 memristor crossbar arrays (0T1R) integrated with CMOS units in external circuits on a single circuit board, demonstrating high complexity110. However, due to the lack of selection function for units in the array, it limits the network scale and reduces the computational accuracy of the network. Compared with the above solutions that prevent crosstalk by adding a transistor (1T1R) to each memristor or by additional operations when there is no transistor, memristors with self-rectifying characteristics do not increase the additional consumption and complexity of the circuit and can effectively avoid crosstalk. They are endowed with natural advantages in information storage and neural synapse simulation. Kanghyeok Jeon et al. have recently successfully integrated self-rectifying memristors into a 1-kb array. The scanning electron microscopy (SEM) image is shown in Fig. 5d. They adopted this array to achieve full-hardware single-layer neural network training and inference, achieving 100% accuracy on the MNIST dataset. They further found that defects in the array (especially open circuit defects) could significantly reduce the classification accuracy since the units at the defect cannot switch correctly, which leads to incorrect array output. The impact of the read range of non-filamentary memristors on accuracy is not significant. This may be ascribed to the fact that although non-filamentary (interface-type) memristors have a smaller read range, the devices exhibit highly consistent operating characteristics and can reliably represent the weights of neural networks, and the output is not unpredictable due to inconsistent memristor behavior108.
With the advancement of technology, the supervised learning neural network memristor array mentioned earlier has been demonstrated multiple times, and the field is gradually developing in other directions, for example, in-situ unsupervised learning of self-organizing maps (SOMs). Rui Wang et al. have experimentally implemented in-situ SOM on memristors based on Ta/TaOx/Pt 1T1R chips for the first time. In an SOM, the Euclidean distance between the input vector and the weight vector is employed to measure their similarity. The smaller the Euclidean distance is, the more similar the two vectors are. During the training process, for a given input, the neuron that is most similar to it (i.e., the smallest Euclidean distance) is found. This neuron is called the Best-Matching Unit (BMU). Subsequently, according to the neighborhood function, the weights of the BMU and the neurons in its neighborhood are updated to make them closer to the current input vector. This process is repeated until the network reaches a stable state. They calculated the Euclidean distance directly in the hardware by adopting an additional 1T1R unit row. The similarity between the input vector and the weight vector can be calculated directly in the hardware without normalizing the weights. They further adopted the memristor-based SOM for data clustering and image processing and solved the traveling salesman problem. The intrinsic physical properties of memristors and the large-scale parallelism of cross arrays make the memristor-based SOM advantageous in terms of computation speed, throughput, and energy efficiency111. In addition, memristor arrays are also being applied to non-neural network fields, such as medical image reconstruction. Han Zhao et al. proposed and experimentally verified a system called “memristive image reconstructor (MIR).” This system is based on memristor arrays for medical image reconstruction, and it performs excellently in terms of energy efficiency and computation speed, and shows high robustness to the non-ideal characteristics of memristors. The MIR system employes the computation method of discrete Fourier transform (DFT), and by computing directly on the memristor array, it greatly reduces the energy-intensive data movement. The paper also proposes a quasi-analog mapping scheme so that the MIR system can more accurately map DFT matrix entries to the conductance of memristors and also uses a complex matrix transmission scheme, so that the MIR system can directly obtain the real and imaginary parts of the DFT result in one step, thus improving the transmission efficiency. In magnetic resonance imaging and computed tomography image reconstruction tasks, compared with Nvidia Tesla V100 GPU, the energy efficiency has been respectively increased by 112 times and 153 times, and the normalized image reconstruction speed has been respectively increased by 36 times and 79 times, which demonstrates the huge application prospects of memristor arrays in medical image reconstruction112.
Volatile
Volatile memristors are gradually developed as spiking neurons applied in neural networks, such as diffusive memristors113 and Mott memristors114. Similar to non-volatile memristors, volatile memristors still need to be integrated with CMOS devices to achieve more complex neuron functions, however, the introduction of memristors significantly simplifies the neuron circuit. Zhongrui Wang et al. adopted diffusive memristors to successfully simulate the function of LIF neurons. The middle layer of this memristor is composed of dielectric materials doped with silver (such as SiOxNy or SiOx). In this model, volatile memristors were employed to simulate ion channels. When there is a signal input, the membrane capacitance begins to charge. If the charge reaches a threshold, the ion channel will be activated, triggering a neural firing to discharge (Fig. 6a). In practical operation process, the device will be excited after a certain number of pulses and will be reset to its initial state after each neural firing (Fig. 6b)115.
Fig. 6. Volatile memristor-based spiking neurons. a, Illustration of an ion channel embedded in the cell membrane near the soma of a biological neuron. b, Experimental plot of the device's response to multiple voltage pulses. Reprinted with permission from ref.115. © 2018 Macmillan Publishers Limited, part of Springer Nature. c, Schematic of habitation in the SNS under the repetition of an identical stimulus (left) and the fully memristor-based artificial SNS circuit (right). d, The habitual behavior of the system under a certain frequency pulse, the pulse emission is from fast to slow. Reprinted with permission from ref.116. © 2020 Wiley-VCH GmbH. e, Schematic of the switching mechanism of the device under different Icc. f, The typical I–V curve of device under Icc of 100 μA (left) and 500 μA (right). Abbreviation: SNS, sensory nervous system. |
In order to attenuate the response of LIF neurons to the same stimulus, volatile memristors are also employed to construct LIF neurons that can adapt to the environment. These neurons could gradually reduce their pulse firing frequency under repeated stimulation of the same signal. Zuheng Wu et al. reported a memristor-based artificial sensory nervous system with habituation characteristics. This system is based on an LIF neuron built with a Mott (Ag/SiO2:Ag/Au) memristor and a LixSiOy memristor synapse (TiN/LixSiOy/Pt), as shown in Fig. 6e (right), which can filter out irrelevant repetitive information and adapt to the external environment. The realization of this function mainly comes from the habituation tendency of the synapse under continuous stimulation, as shown in Fig. 6c (left), so that the output of the neuron presents a frequency-drop characteristic (Fig. 6d). The process is shown in Fig. 6e. In the initial state, the synapse is in an HRS (i) since the lithium silicate film is in a low-conductivity amorphous state. When applying a positive voltage to the device under a lower limiting current (100 μA), a CF composed of crystalline lithium silicate will be formed, causing the device to switch from an HRS to an LRS (ii). Due to insufficient Joule heat, the filament is difficult to be melted, instead, a negative voltage is required for destroying the filament. However, at a higher current (500 μA), a crystalline filament that can increase the conductivity (iii) will be formed firstly, and then the filament tends to break under the Joule thermal effect, which results in a decrease in conductivity (iv) and an accompanying decrease in response. The two situations correspond to the I-Wiley-VCH curves in Fig. 6f 116. This kind of indirect method for adapting to the environment puts higher requirements on the synapse. Rui Yuan et al. designed a high-efficiency neuromorphic detection system based on VO2 memristors, which can directly implement adaptability in LIF neurons. This system contains mainly two major modules: coding and information processing. In the coding segment, they designed an asynchronous encoder that can pulse encode the increment of analog signals based on the highly symmetrical volatile-threshold resistive switching characteristics of VO2 memristors (Fig. 7a [top]), and the pulse sequence after encoding has high sparsity and minimizes loss of information (Fig. 7a [bottom]). In the neuronal signal processing segment, not only have LIF neurons been constructed using VO2 memristors (Fig. 7b [top right]), but an adaptive version of these neurons, known as Adaptive Leaky Integrate-and-Fire (ALIF) neurons, has also been designed (Fig. 7b [left]). Under signal stimulation, these ALIF neurons initially maintain a high frequency, which then decreases and stabilizes at a lower level (Fig. 7b [bottom right]). Ultimately, both LIF and ALIF neurons have been integrated into a long- and short-term memory spiking neural network (LSNN). The detection system based on an asynchronous encoder and LSNN shows excellent computing power, and only a small network is required to achieve a quite high accuracy in physiological detection117. However, the adaptive function of the ALIF neuron is derived from the peripheral CMOS circuit. In contrast, Haowei Wang et al. realized the adaptive function without changing the LIF neuron circuit structure. They used an Ag/Ti/GaSe/Pt/Ti memristor with a threshold switch function to make an LIF neuron of adaptive function. Under a constant pulse sequence, the pulse triggering frequency in this neuron continuously and adaptively decreases to a stable level (Fig. 7c)118. Besides, Jianhui Zhao et al. made a light-sensitive NdNiO3 volatile-threshold switch memristor that responds to the variation of light intensity, and its I-V curve is shown in Fig. 7d. Based on this device, an LIF neuron with a light-intensity-dependent firing frequency has been fabricated, without the need for additional light sensors in the circuit119.
Fig. 7. Volatile memristor-based spiking neurons. a, Circuit schematic of memristor-based asynchronous spike encoder. b, Circuit schematic of the VO2 memristor-based ALIF neuron. Reprinted with permission from ref.117. © 2023 The Author(s). c, Spike frequency gradually decreases with time under different inputs. Reprinted with permission from ref.118. © 2023 IEEE. d, I–V characteristics for different light intensities. Reprinted with permission from ref.119. © 2023 Royal Society of Chemistry. Abbreviation: ALIF, Adaptive Leaky Integrate-and-Fire. |
Apart from being used as neuron components, volatile memristors can also be widely used as selectors in synaptic arrays to suppress sneak currents. For example, Moonkyu Song et al. inserted a single-layer defect graphene between the Ag electrode and the Al2O3 interlayer. The defect pores in graphene restrict the migration of Ag cations and the size of Ag CFs, which leads to the self-compliance of the selector without the need for additional CMOS devices120. Moreover, Qilin Hua et al. prepared threshold-switching selectors that showed high selectivity (greater than 108), high conduction current (greater than 100 μA), and high durability (108) through rapid thermal processing. The selector can maintain stable switching even at 200 °C121.
ALGORITHMIC OPTIMIZATION BASED ON MEMRISTORS
Constrained by the inherent characteristics of memristors and current fabrication technology, the space for optimizing device performance through process and technology is limited. However, the application potential of memristors can be fully explored by directly adopting non-ideal memristors or designing specific algorithm structures for non-ideal characteristics.
Memristors with good symmetry and linear conductance regulation can improve the accuracy of ANN simulation122, but the conductance curve of real memristor devices often fails to meet the requirements. Some researchers have found that SNN has a strong tolerance for the non-linearity of the device (Fig. 8a). Algorithm simulation results show that as long as the memristor has a symmetrical LTP and LTD curve or a positive long-term potentiation (LTP) and long-term depression (LTD) non-linearity factor (the positive and negative nonlinearity factors are shown in Fig. 8b), the network can maintain high accuracy, and the actual manufactured memristor can meet the requirements of positive LTP and LTD non-linearity factors. This means that SNNs can directly use asymmetric and non-linear memristors as synapses123. On the other hand, synapses in the SNN network often have a large number of weights with different values, and the existing memristor only has a limited number of conductance states. Even the currently most outstanding memristor has achieved 211 conductance states with high-precision tuning124, but the complexity of regulation and the reliability of the device after programming cannot be ignored. Nitin Rathi et al. can not only reduce the network through the algorithm of sparse SNN topology but also adapt to the limited conductance state of the memristor. Its schematic diagram is shown in Fig. 8c. The sparsity comes from pruning, and the use of a weight-dependent STDP model which will retain or delete synaptic connections based on the pulse correlation of the front and rear neurons, will retain synaptic connections with stronger weights, and prune other synaptic connections. In order to adapt to the limited conductance state of the memristor, the synaptic weight of the retained connection is quantized to the available conductance state. In the training process, the network is pruned and quantized every training period to achieve the purpose of sparse SNN topology. Training results show that sparse SNN topology has the same classification accuracy as FC SNN topology with lower energy consumption125. For non-volatile memristors, HRSs and LRS (binary) are considered as the most stable and least random states. Therefore, non-volatile memristors demonstrate the potential to develop into commercial memory126. In order to take full advantage of the excellent performance of memristors and avoid the challenge of resistance state instability in neuromorphic hardware, two-state nonvolatile memristors tend to be attractive options for implementing neural network hardware. Binary neural networks (BNNs) are the products of quantizing weights of DNNs and have demonstrated great application potential127-132. In BNNs, network weights and neuron activations are limited to be −1 or 1, which greatly reduces the demand for conductance quantity and is compatible with non-volatile memristors. In addition, with the use of bit operations (such as XNOR) instead of arithmetic operations, the algorithm efficiency can be significantly improved by BNNs. The concept of BNNs is also introduced to develop hardware-friendly binary SNNs (BSNNs). During the training process, BSNNs use surrogate gradient methods to replace the derivatives of spike training, and binarize the weights. In BSNNs, the input/output and the activation values of neurons in SNNs are all binary. Such a simplification treatment significantly reduces the requirements for memristor performance and renders the memristor hardware to have a great practical application potential for bit-operation inference, which is conducive to the integration of large-scale neuromorphic hardware. After training, BSNNs showed excellent recognition accuracy on dynamic image datasets N-MNIST and DVS-CIFAR10, dynamic gesture dataset DvsGesture, and dynamic audio dataset N-TIDIGITS18133,134. In the implementation of BSNNs, a memristor synapse array that performs XNOR operations can be adopted to implement its computing core. This method of adoping logical operations (such as XNOR) has been successfully demonstrated in many studies135,136. However, the binarization of weights sacrifices the precision of a single synapse, which inevitably leads to an increase in both the network scale and the energy consumption.
Fig. 8. Memristor-based algorithm optimization. a, The final accuracy for 121 different cases of LTP and LTD. Reprinted with permission from ref.123. © 2021 Authors. S.A. b, The weight-update curves (different non-linearity factors). c, SNNs topology with lateral inhibition. Reprinted with permission from ref.125. © 2019 IEEE. d, Diagram of the STELLAR architecture used in the memristor chip. Reprinted with permission from ref.137. © 2023 American Association for the Advancement of Science. e, Flowchart of the hybrid-training method (left) and diagram of the demonstration with hybrid training (right). Reprinted with permission from ref.107. © 2020 The Author(s), under exclusive licence to Springer Nature Limited. Abbreviations: LTD, Long-Term Depression; LTP, Long-Term Potentiation; SNNs, spike neural networks. |
In addition to the limited number of conductive states, many other non-ideal characteristics of memristors can be mitigated by designing specific network topologies to reduce their impact on hardware networks. Wenbin Zhang et al. proposed the STELLAR algorithm architecture that can adapt to device non-idealities and confirmed its excellence on a fully integrated memristor chip. On the condition of ensuring learning capabilities, this architecture could achieve about 75 times higher energy efficiency than the digital accelerators. It is designed as a universal method suitable for different neural network structures. This algorithm does not use a write verification scheme but tunes the memristor without verification, making the hardware adapt to the non-linearity and asymmetry of the device. This could be ascribed to the fact that the computational modules on the chip do not perform precise weight calculations but are adopted to determine the update direction of the weight memristor cross array. For a two-layer network, the update direction only depends on the signs of the first-layer output, the second-layer output, and the error. After the direction is determined, the same SET or RESET voltage pulse is applied to the memristor unit. At the same time, a configurable threshold is introduced for adapting to different learning tasks. This threshold can filter out small error values, avoid too frequent weight updates and oscillation states of the network, and improve the convergence of the algorithm. This process is depicted in Fig. 8d. During the forward inference phase, the vector-matrix multiplication operation is performed using the memristor cross array to obtain the output vector of the network, where, X denotes the input vector, Y1 is the output vector of the first layer, Y2 is the output vector of the second layer, and W1 and W2 represent the conductance weight matrices of the first and second layers, respectively. In the weight-update phase, the error vector E is firstly calculated with the adoption of the target vector T and Y2, and the error sign SE is extracted under the influence of the configurable threshold. Combined with the sign vector SY1 of the first layer output and the sign vector SY2 of the second layer output, the weight update ΔW2 is calculated in a row-parallel manner using cyclic parallel conductance tuning137. Various non-ideal characteristics of memristors can also be avoided through hybrid training algorithms. As shown in Fig. 8e, the model is firstly trained in software through ex situ training to obtain high-precision weights. Subsequently, these weights are quantized and mapped to the memristor cross array. This step will lead to accuracy loss, and errors in the mapping will be caused due to the non-ideal characteristics of the memristor, such as randomness, drift, etc. Finally, in order to compensate for the errors introduced by quantization and device non-ideal characteristics, the last FC layer is trained in situ using part of the data. In situ training uses the memristor-based neural processing unit to calculate output data, compares it with the label to get the error signal, and then inputs it into the error BP module to generate the corresponding pulse sequence with the learning rate, which is used to adjust the memristor conductance value of the FC layer until the entire system reaches the preset accuracy or times107. When mapping network weights to large memristor arrays, issues such as latency and energy consumption need to be taken into consideration. Shared buses can cause basic latency and energy bottlenecks in large neuromorphic hardware. The SpiNeMap design algorithm138, which maps SNNs to neuromorphic hardware based on crossbars, can minimize peak latency and energy consumption. Compared with the best-performing SNN-mapping technology, SpiNeMap could reduce the average energy consumption by 45% and peak latency by 21%. Some energy-saving reconfigurable architectures have also been proposed, such as RESPARC for deep spiking neural network memristor arrays. As shown in Fig. 9a, when using CNN and MLP topologies, for the three datasets MNIST, SVHN, and CIFAR-10, energy consumption and performance acceleration were normalized. The results show that, for CNNs, the average energy consumption is reduced by 12 times, and the performance acceleration is 60 times. For MLPs, the average energy consumption is reduced by 513 times, and the performance acceleration is 382 times139. These computing architectures can better map weights to memristor arrays with non-ideal characteristics to improve the efficiency and practicality. However, in-situ learning algorithms can avoid weight mapping and also improve the network's tolerance to non-idealities. For example, Can Li et al. built an in-situ learning multilayer neural network based on hafnium oxide memristor arrays (1T1R), which proves this point. They firstly applied a positive pulse to the bottom electrode of the memristor to initialize the array, and subsequently applied synchronous positive-voltage pulses to the top electrode of the memristor and the gate of the series transistor to change the conductance state of the memristor. Since the limiting current of the memristor is controlled by the gate voltage of the transistor, this scheme for regulating conductance can achieve linearity and symmetry of the conductance value while reducing the conductance changes between cycles and devices. This in-situ learning hardware network employs stochastic gradient descent for training and can achieve a classification accuracy of 91.71% on the MNIST dataset, which is close to the defect-free simulation results. Importantly, the training algorithm assumes that all the devices are pulse-programmable, and 11% of the devices in the memristor array are unresponsive to pulses (the typical defect value ratio observed in the experiment), which fully demonstrates that in-situ learning can adapt to hardware defects. The specific results are shown in Fig. 9b and c. It can be found in Fig. 9b that the in-situ training process adapts to defects and provides higher defect tolerance compared to networks that load offline training weights. Even if 50% of the devices are in a defective state, the network can still achieve an accuracy rate of 60%. In Fig. 9c, the tolerance of device defects for in-situ training of multi-layer and single-layer networks is compared. It is found that multi-layer networks are more conducive to improving defect tolerance. This may be attributed to the fact that when the network scale increases, in-situ training can provide better adaptability to reduce the accuracy drop caused by defective units105.
Fig. 9. Optimization of memristor-based algorithm performance diagram. a, Comparison of energy savings and performance speedups obtained per classification for RESPARC over the CMOS baseline for various SNNs applications with CNN and MLP topologies. Reprinted with permission from ref.139. © 2017 ACM. b, The impact of non-responsive devices on the inference accuracy with in situ and ex situ training approaches. c, Comparison of defect tolerance between the multilayer network with and the single-layer network in situ training. Reprinted with permission from ref.105. © 2018 The Author(s). d, Performance improvement (accuracy and AUROC) brought by weight noise injection (WNI) under different conductance ranges and variation coefficients. Reprinted with permission from ref.140. © 2021 IEEE. Abbreviations: AUROC, area under the receiver operating characteristic curve; CMOS, complementary metal–oxide semiconductor; CNN, convolutional neural network; MLP, multilayer perceptron; SNNs, spike neural networks. |
There are other methods to alleviate the performance degradation brought by the non-ideal characteristics of memristors to the network. For example, a method called weight noise injection (WNI) is introduced in the algorithm. This method simulates the random fluctuations generated by memristors during conductance switching by adding noise to the weights during training. The noise comes from the random distribution of memristor devices. In this way, the network can adapt to the non-ideal characteristics of memristors during training, thereby maintaining high performance when mapped to hardware. Fig. 9d shows the performance improvement (accuracy and area under the receiver operating characteristic curve values) of the WNI method on the MNIST and performance measurement system (PeMS) data under different conductance ranges and variation coefficients. When the variation on the MNIST data is 40% and the normalized distance of high and low conductance is 0.5, 10% improvement can be achieved by the network accuracy. However, the improvement on the PeMS data is not as significant as that on MNIST (3.3%), which could be attributed to the limited space for improvement140. This non-ideal randomness can also be utilized. For example, Parami Wijesinghe et al. combined random memristors with other circuit elements (such as capacitors, transistors, etc.) to construct a spiking neuron with a random activation function. By combining it with a memristor array to form a circuit unit, and then stacking multiple circuit units together, a deep random SNN was formed. In order to support the random activation function provided by the memristor, they proposed a support algorithm to determine the voltage and current of each layer based on the input and output signals of each layer, ensuring that each memristor neuron can work normally and minimize the energy consumption as much as possible. The final result shows that the accuracy of the all-memristor deep random SNN in image classification is equivalent to that of ANN, but it saves about 6.4 times the energy of CMOS hardware. Moreover, the introduction of this random neuron is conducive to improving the robustness and generalization ability of the neural network141.
CHALLENGE
In spite of the fact that the SNNs have been theoretically demonstrated to exhibit good computational capabilities equivalent to Turing machines142, their training remains challenging due to the non-differentiability of the activation function, which makes the BP algorithm inapplicable. Rule-based training methods, for instance STDP, are applicable, however, it still remains a formidable challenge to train a deep SNN. In many reported spiking networks based on STDP, training is usually confined to a single layer143,144. In contrast, various optimization-based methods have enabled the use of BP for training in SNNs, yielding commendable results. However, BP is not only biologically implausible but also has other limitations, such as the necessity for extensive adjustments and optimizations using the BP algorithm, which may not always be feasible or efficient in practical applications and hardware implementations. Therefore, more efforts focused on developing efficient and practical training methods are required to better exploit the potential of deep SNNs. This includes developing new learning rules and optimization strategies, as well as exploring how to integrate SNNs with other types of neural networks (such as CNNs or recurrent neural networks), which facilitates the application of SNNs in a broader range of tasks145.
From the perspective of network accuracy, even the most advanced SNN training methods currently available cannot produce the competitive accuracy comparable to ANNs (for example, variants of BP in SNNs). This can be attributed to the fact that information loss occurs in the process of converting information into spikes within a finite time window, so SNNs are usually at a disadvantage in tasks designed for ANNs. Currently, there is a lack of appropriate benchmark data for evaluating SNNs. Ideally, SNNs should always be evaluated on event-based datasets, where they can surpass ANNs by leveraging the spatiotemporal information encoding of event streams146. For example, in autonomous driving or robot-vision systems, event cameras can provide visual inputs with high temporal resolution and high dynamic range, and SNNS can efficiently process these inputs to perform a variety of tasks that traditional ANNs cannot accomplish, such as feature detection, optical flow calculation, scene reconstruction, image segmentation and object recognition. In addition, since event cameras only produce output when brightness changes, their power consumption is much lower than that of the traditional cameras. This makes them very suitable for applications that need to run for a long time or are battery-powered147. In addition, even if the same dataset is used, the differences in frameworks148,149 and hardware platforms make it difficult to compare the pros and cons between different systems. Relevant articles provide benchmark testing methods33, which can evaluate the quality of different networks and hardware systems, but further optimization is still needed.
At the aspect of hardware integration, large-scale passive cross memristor synapse arrays are faced with two insurmountable obstacles, that is, sneak current and IR drop. The sneak current problem will reduce the reading accuracy of the array, while the IR drop problem stems from the need for a larger writing voltage to rewrite the conductance state of the device when the wire is scaled down to the nanoscale. This larger writing voltage brings many restrictions, for example, its writing scheme (V/2 or V/3) prohibits a significant increase in writing voltage89. The sneak current problem can be reduced by increasing the nonlinearity of the device unit itself or by integrating a memristor with a strong non-linear element (such as a transistor) to suppress sneak current150,151. The IR drop problem can be attenuated by adopting a higher-resistance memristor to avoid the voltage drop resulted from the reduction of electrode size (this will limit the reading speed, so it needs to be considered comprehensively). However, these patches will significantly increase the cost and complexity. As an alternative, two-terminal structures metal-insulator-metal (MIM), threshold selectors152,153, and memristors with self-rectification effects deserve more attention154. At the same time, new design strategies and architectures also need to be explored continuously so as to overcome the challenges existing in the design process of large-scale passive cross-memristor synapse arrays.
At the aspect of devices, there exist differences in properties between the real and ideal devices, and among real devices themselves, all these inevitably impact the network155. Among them, the difference in the same storage unit from cycle to cycle and that in different storage units on the same chip are the biggest challenges that limit the development of this field156, although this also brings some opportunities, such as using randomness for encryption157. It is currently believed that the difference in memristors from cycle to cycle is ascribed to the randomness of the CF mechanism, so memristors based on non-CF-switching mechanisms are worthy of more attention in the future. The difference in storage units on the same chip, which can be attributed to the randomness, may also be ascribed to the unevenness introduced during the manufacturing process. This requires exploring new processes and manufacturing methods to reduce the differences on the same chip158.
In short, memristor promises a very broad application prospect in neuromorphic computing. They can simulate neurons and synapses, and simultaneously build complex neural network structures to achieve advanced functions such as in-situ learning and pattern classification. However, both the algorithm and the memristor hardware face their own challenges. Optimizing only one aspect cannot implement SNNs on hardware and fully exploit their potential. Therefore, development of customized algorithms that can maximize their performance based on the inherent attributes of memristors is highly desired. Only in this way can we fully utilize the unique properties of memristors on the basis of deep understanding, thereby building more efficient and powerful neuromorphic computing systems.
CONCLUSION
As the latest generation of neural networks, SNNs work in a pulse-based event-triggered operating mode that ensures their low energy consumption. Undoubtedly, hardware implementation of neural networks is one of the main pathways towards lower-energy-consuming SNNs, which involve not only superior device structures but also well-matched algorithm models. Based on the current progress of neural networks and memristor devices, a detailed analysis on algorithm optimization for memristors has been performed, and the challenges faced at the algorithm and hardware levels were also summarized. This key area involves, on the one hand, determining the performance requirements of memristors through algorithm simulation, and on the other hand, designing dedicated network topologies for memristors in turn. This algorithm development based on the inherent attributes of memristors will promote the further development of SNNs and achieve a higher level of performance. This is a challenging but promising field. SNNs are expected to achieve more biologically reasonable and efficient neuromorphic systems, thereby promoting cutting-edge researches in neuroscience and computation.
MISCELLANEA
Declaration of competing interest The authors declare no competing interests.
