INTRODUCTION
The tendency of very-large-scale integration (VLSI) has been prompting higher demands on static random-access memory (SRAM) devices, therefore it is of great urgency to develop SRAM with higher density and lower standby power1-8. However, there are many limitations for conventional 6T-SRAM cell that is no longer able to meet the requirements of outstanding performance and high integration simultaneously9-16. Other complementary metal oxide semiconductor (CMOS)-based SRAM topologies, such as 7T17, 8T18, 9T19, and 10T20, have been enhanced by improving the design, but this has also led to an increase in cell area, which is not conducive to integration21.
Since the last century, tunneling-based SRAMs (TSRAMs) have emerged22-27. As shown in Fig. 1a, based on a pair of tunneling devices with negative differential resistance (NDR) behavior, the TSRAMs could realize read and write operations by applying different bias voltages to control the tunneling current so as to switch between the two stable operation points, denoted by “0” and “1”28. At present, there are mainly two topologies for TSRAMs, besides the tunneling device pair, one of the designs consists of one additional transistor (Goto-type SRAM cell22, shown in Fig. 1b), while the other contains one transistor and one capacitor (dynamic random-access memory (DRAM)-like cell23, shown in Fig. 1c). Compared with CMOS-based SRAMs, TSRAMs are significantly smaller in size, which contributes to higher density, and they also exhibit lower standby power and better performance29,30.
Fig. 1. Load-line diagram and topologies of tunneling-based SRAMs. a, Load-line diagram of a tunneling-based SRAM. b, Schematic of a Goto-type SRAM cell. c, Schematic of a DRAM-like SRAM cell. Abbreviations: DRAM, dynamic random-access memory; SRAM, static random-access memory. |
The concept of TSRAM has been proposed in the last century. Nevertheless, among previous tunneling devices that are available for TSRAM, PVCR of Esaki tunneling diodes (TDs) is too small31-33, while resonant tunneling diodes (RTDs) have to rely on superlattice constructed by III-V compound semiconductor23,34, which is not quite compatible with the mainstream silicon technology, thus causing difficulty for manufacture. Both of these factors have restricted the application potential of TSRAMs.
In 2022, Wu et al. proposed a novel tunneling device called the cross-coupled gated tunneling diode (XTD)35, which could also exhibit NDR behavior, with a much higher PVCR than Esaki TD. As shown in Fig. 2a, the major part of an XTD includes a tunnel junction with two gate electrodes. Unlike Esaki TD, XTD operates in the reverse bias direction, leading to a difference in operation mechanism and performance between them. Fig. 2b shows the operation mechanism of an XTD when applying an external reverse bias, quasi-Fermi level (QFL) in the n-doped region will move downward while QFL in the p-doped region will be raised. If the reverse bias voltage is not very large, the conduction band (CB) of the n-doped region and the valence band (VB) of the p-doped region will be overlapped, contributing to significant band-to-band tunneling effect and thus great tunneling currents. On the condition that the gates G1 and G2 don't exist, band overlap between n-doped and p-doped regions, or the so-called tunneling window will keep expanding. However, since G1 and G2 are respectively equipotential to the n-doped and p-doped regions, this leads to band bending near the gated regions controlled by G1 and G2. After the bias voltage exceeds a critical point, the tunneling window will be gradually turned off with the tunneling current decreasing significantly, and therefore the NDR effect could be observed.
Fig. 2. Schematic and operation mechanism of an XTD. a, Schematic of an XTD. b, Band diagrams of an XTD under different bias voltages, where, V1 < V2 < V3. Abbreviations: XTD, cross-coupled gated tunneling diode. |
Due to the reverse bias applied to XTD, the thermionic emission36 and trap-assisted tunneling (TAT) effects37 under high voltage are suppressed, so the valley current of XTD could be extreme low, which results in a PVCR of beyond 105,35. Furthermore, with such an XTD device, Wu et al. designed a Goto-type SRAM cell (XT-SRAM) with its performance tested under HSPICE simulation. Compared with the conventional 6T-SRAM, XT-SRAM tends to exhibit outstanding advantages as its area is reduced to 1/8, standby power declined to 1/70, with much lower read and write latency38. Because of its high PVCR and excellent performance, the XTD proposed by Wu et al. shows greater application potential than TD and RTD in the area of high density and low standby power of SRAM devices. Yet, in the work conducted by Wu et al., a biaxially strained Ge/Si heterojunction was adopted as the tunnel junction35, and some technical challenges still exist.
In the current work, more detailed discussion about XTD was conducted, and the application potential of XTD devices will be further explored through technology computer aided design (TCAD) simulations. To research the compatibility of XTD with mainstream Si technology, a Si XTD design whose tunnel junction is formed by a heavily doped silicon pn junction was proposed by referring to the work of Wu et al.35. By performing TCAD simulation with the Si XTD model, the NDR behavior of such device was validated, and high PVCR up to 104 was observed. Subsequently, the influence of different device parameters, such as doping concentration and depth was also discussed. Then, the performance of Si XTD devices under different device parameters and the range of device parameters for Si XTD devices with ideal performance were given. And finally, to illustrate the performance of such devices in TSRAM, SPICE simulation for a TSRAM cell based on Si XTD was also conducted to illustrate the performance of such devices in TSRAM.
TCAD SIMULATION AND VALIDATION OF SI XTD
As shown in Fig. 3a, by slightly adjusting the Si/Ge heterojunction XTD in ref.35, the Si XTD model used for TCAD simulation is obtained. Therein, the Si/Ge heterojunction with a doping depth d = 4 nm is replaced by a heavily doped Si pn junction, and the doping concentration of n-doped and p-doped regions is raised. In addition, a low-doped silicon substrate of 100 nm is introduced to model a Si XTD that is fabricated on bulk silicon or SOI substrate. High-k materials such as HfO2 still need to be adopted for dielectric layers of gates G1 and G2. In order to lower the parasitic capacitance between the gates, an air gap between them is necessary. According to field effect transistor (FET) conventions, the electrodes of p-doped and n-doped regions are labeled as source (S) and drain (D), respectively.
Fig. 3. Results of TCAD simulation for a Si XTD. a, Schematic of a Si XTD. b, I-V characteristics of the Si XTD, in linear (lin) and logarithmic (log) scales. c, I-V characteristics of the Si XTD, without the gates G1 and G2, in linear (lin) and logarithmic (log) scales. d, Band diagrams of a Si XTD under different bias voltages. Abbreviations: Si XTD, silicon cross-coupled gated tunneling diode; TCAD, technology computer aided design. |
It should be noted that such an adjustment may seem like a simple change from the Si/Ge XTD in ref.35 to our Si XTD, but it makes a huge difference between technology and cost. To fabricate such a Si/Ge XTD in ref.35, a Si1-yGey virtual substrate should be firstly grown on bulk silicon substrate, subsequently the biaxially strained Si/Ge heterojunction is grown on the virtual substrate with the adoption of the complicated epitaxy growing methods such as molecular beam epitaxy (MBE) or ultrahigh-vacuum chemical vapor deposition (UHVCVD)39,40. Due to the complexity of these processes, it will be quite costly and challenging to manufacture Si/Ge XTDs. Instead, to fabricate a Si XTD in Fig. 3a, the mainstream silicon technology is probably needed, which costs much less than those epitaxy growing methods and is suitable for mass production. Therefore, it is necessary to investigate the feasibility of Si XTDs.
With the design shown in Fig. 3a, the I-V characteristics of the Si XTD are simulated by Cogenda TCAD41. During the TCAD simulation, S and G2 are both grounded, while an external voltage VD up to 1.5 V is applied to D and G1. The dynamic nonlocal path band-to-band tunneling model is used, and the TAT effect is also included.
The I-V characteristics of the Si XTD are shown in Fig. 3b on a linear and logarithmic scale, where typical NDR behavior could be observed. The peak current of the Si XTD is Ipeak = 2.06 × 10−10 A μm−1 (since 2D simulation is performed) at VD = 0.42 V, while the valley current is Ivalley = 9.84 × 10−15 A μm−1 at VD = 1.38 V, resulting in a PVCR of 2.09 × 104 for the silicon XTD. Therefore, the Si XTD with similar structure to the Si/Ge heterojunction XTD in ref.35 still shows significant NDR behavior, but it is noticed that the peak current decreases greatly for the Si XTD.
Band diagrams of the Si XTD under different bias voltages in the simulation are shown in Fig. 3d, which are extracted from the bottom of the doped layer. When VD = 0 V, the valence band maximum (VBM) of the p-doped region and the conduction band minimum (CBM) of the n-doped region are almost aligned due to heavy doping in both regions, but there is no tunneling window at this time. With rising VD, band overlap between p-doped and n-doped regions appears, and the tunneling window also keeps broadening. Since the potential of the gate electrode in p-doped region, G1, is higher than that of the source, the energy band near the region controlled by G1 bends downward, and the energy band near the region controlled by G2 bends upward correspondingly. As VD continues to increase, band bending resulting from G1 and G2 tends to be greater, which makes the tunneling window shrink gradually instead. Band diagrams of the Si XTD under different bias voltages exhibit a very similar trend to the ones of Si/Ge XTD in ref.35, suggesting that both of them work in the same way. It is validated in Fig. 3c that the Si XTD not only shows the NDR behavior, but also exhibits high PVCR, i.e., the gated NDR effect35 is also possible to be observed in a heavily doped Si pn junction.
To further explain the role of the double-gate structure and verify its importance, another TCAD simulation is performed on the Si XTD in Fig. 3a, but the gates G1 and G2 are excluded. As shown in Fig. 3c, the current through the device ID keeps rising with increasing external voltage VD, showing no NDR effect at all, and the result is predictable. As is described in the introduction part and Fig. 3d, the gates G1 and G2 are designed to control the energy band near the junction interface, which could gradually turn off the tunneling window after VD exceeds a critical point. Here in Fig. 3c, due to the absence of the gates G1 and G2, the Si XTD degenerates into a simple heavily doped Si pn junction, with reverse bias applied. While the reverse bias voltage VD is increasing, the tunneling window also keeps broadening, thus, the tunneling current ID that keeps growing could be observed in simulation. From another aspect, the result in Fig. 3c also illustrates that the double-gate structure serves as the core role in Si XTD.
For the peak current of the Si XTD in Fig. 3a, Ipeak = 2.06 × 10−10 A μm−1 is obtained from 2D simulation, which takes the vertical size of the device's channel into consideration (i.e. the depth of the doping layer, d = 4 nm). The peak current density of the device should be approximately in the order of a few A cm−2. Such current density is somewhat too small, so this Si XTD may not be suitable for Goto-type SRAM cells, which require a large peak current density in excess of 104 A cm−2, but it could still be applied in DRAM-like TSRAM cell8. Owing to high PVCR of the Si PVCR, a TSRAM made of such device is possible to achieve ultralow standby power. On the other hand, such Si XTD is totally compatible with the main Si technology. Therefore, Si XTD may be a practical silicon tunneling device and offer great application potential.
DISCUSSION ABOUT DEVICE PARAMETERS AND PERFORMANCE
The Si XTD concept proposed in the current work has been validated in the last section. In this section, further TCAD simulations will be performed to investigate the influence of different device parameters on the performance of Si XTD, as shown in Fig. 3a. And the range of device parameters for Si XTD is also explored, where decent performance is likely to be achieved. Here, the device parameters of interest are the gap distance between gates G1 and G2 (Lgap), the depth of doping layer (d), and the concentration of p-doped and n-doped regions (Na and Nd). In the simulations, only the device parameters above will be changed and the others are the same, as shown in Fig. 3a.
Influence of Lgap
I-V characteristics of several Si XTDs with different Lgap are shown in Fig. 4a, where, d = 4 nm, Na = 3.5 × 1019 cm−3, Nd = 4.0 × 1019 cm−3. As Lgap increases, the peak and valley currents of Ipeak and Ivalley tend to increase significantly, and the corresponding drain voltages Vpeak and Vvalley also show a slight increasing trend. When Lgap is short, the increment of Ivalley is greater than that of Ipeak, resulting in a decrease of PVCR. If Lgap is longer than a critical value, no valley will be observed in the I-V curve even if VD is risen up to 1.5 V, which means that PVCR of the device is quite low. For these Si XTDs, there exists a different Lgap, the distance between the end of one gate and the pn junction is fixed. When Lgap grows, the range of regions controlled by gates or the effective length of the channel is reduced, leading to the reduction of PVCR, which is similar to how Lch willinfluence PVCR in ref.35. Therefore, in order to achieve high PVCR and low operating voltage VDD, Lgap should be chosen as short as possible. However, to avoid a Si XTD with too small Ipeak, Lgap should not be too short, the limitation of process should also be taken into account. Since a quite small Lgap (less than 14 nm) is required for a practical Si XTD, an advanced CMOS process may be needed to fabricate such devices.
Fig. 4. Influence of different device parameters on Si XTD. a, I-V characteristics of Si XTDs with different gap distance (Lgap). b, I-V characteristics of Si XTDs with different doping depth (d). c, I-V characteristics of Si XTDs with different acceptor concentrations (Na). d, I-V characteristics of Si XTDs with different donor concentrations (Nd). Abbreviations: Si XTD, silicon cross-coupled gated tunneling diode. |
Influence of d
I-V characteristics of Si XTDs with different d are shown in Fig. 4b, where, Lgap = 7 nm, Na = 3.5 × 1019 cm−3, Nd = 4.0 × 1019 cm−3. Similar to the impact of Lgap, an increase of d leads to a significant increment of Ipeak and Ivalley, meanwhile Vpeak and Vvalley tend to grow slightly. It can be seen that a practical Si XTD requires an appropriate d. A too small doping depth is not only technically difficult to achieve, but also leads to weak Ipeak. On the other hand, if d reaches beyond 5 nm, PVCR of a Si XTD will decrease dramatically. Since the impact of variations in d on a Si XTD is very strong, a mere 0.5 nm shift will make a difference to Ipeak of roughly one order of magnitude, which suggests that the realization of a practical Si XTD needs ultra-shallow junction technology with high accuracy.
Influence of Na and Nd
I-V characteristics of Si XTDs with different Na and Nd are shown in Fig. 4c and d, where, Lgap = 7 nm, d = 4 nm, the corresponding Nd and Na are 4.0 × 1019 cm−3 and 3.5 × 1019 cm−3, respectively. Whether donor or acceptor, an increase in doping concentration will contribute to significant growth of Ipeak and Ivalley. As Eq. (1) implies, the wider the tunneling window ΔΦ is, the higher the tunneling probability TWKB will be42. In addition, as shown in Fig. 2b, high doping concentration tends to bring more band overlap between the p-doped and n-doped regions, which results in a wider ΔΦ, so high doping concentration is conducive to large tunneling current. From Fig. 4c and d, it is clear that too low doping concentration will lead to a small Ipeak, while high doping concentration will result in the increment of operating voltage VDD. Therefore, to achieve a Si XTD with ideal performance, appropriate doping concentrations Nd and Na should be chosen.
$T_{\mathrm{WKB}}=\exp \left(-\frac{4 \lambda \sqrt{2 m^{*} E_{\mathrm{g}}^{3}}}{3 \hbar\left(\Delta \Phi+E_{\mathrm{g}}\right)}\right)$
Influence of junction-interface offset
For the design of the Si XTDs in the current work, the pn-junction interface is supposed to be exactly at the center of the device, which is quite hard to achieve during the actual process. Thus, the offset of the junction interface should be taken into account. As shown in Fig. 5, Si XTDs with various xoffset exhibits different I-V characteristics, while other device parameters include Lgap = 5 nm, d = 4 nm, Nd = 3.0 × 1019 cm−3 and Na = 4.0 × 1019 cm−3. On the one hand, Fig. 5 illustrates that the presence of xoffset can result in degeneration of device performance such as PVCR, and the larger xoffset is, the lower PVCR will be. On the other hand, while a xoffset in a Si XTD may always be unavoidable for the actual process, Fig. 5 also implies that the performance degeneration brought by a xoffset, which is small enough, is tolerable. For example, in the case of Fig. 5, even if xoffset reaches half of Lgap, which means that the junction interface has been aligned with the right edge of G1, and PVCR decreases to about 30% of the original, the performance of the device is still acceptable with a PVCR on the order of 104. In other words, a small error or offset during the process will not cause failure in the device.
Fig. 5. Influence of junction-interface offset on Si XTD. a, Schematics of Si XTDs with different junction-interface offset (xoffset). b, I-V characteristics of Si XTDs with different xoffset. Abbreviations: Si XTD, silicon cross-coupled gated tunneling diode. |
Overall performance of Si XTDs
Next, the range of performance for Si XTDs with various device parameters is further explored through TCAD simulations, where, different combinations of Lgap, d, Na and Nd will be tested out. In the simulations, the values of Lgap are set as 5, 7, 10, 14 nm, depths of the doping layer d set as 3, 3.5, 4, 4.5, 5 nm, the values of Na taken as 3.0, 3.5, 4.0, 4.5, 5.0 × 1019 cm−3, and the values of Na taken as 2.5, 3.0, 3.5, 4.0 × 1019 cm−3. Simulations before have shown that our Si XTDs are not suitable for Goto-type SRAM cell shown in Fig. 1b, but are able to be applied in DRAM-like TSRAM cell shown in Fig. 1c instead. As mentioned in ref.28, such devices require a peak current density of at least 1 A cm−2, i.e., for our Si XTDs, the Ipeak in the simulations should be no less than 10−10 A μm−1. To realize desirable performance such as low standby power, PVCR of a Si XTD in the simulations should exceed an order of 103,28. Therefore, among all of the simulated Si XTDs, only the ones with an Ipeak of above 10−10 A μm−1 together with a PVCR of above 103 are taken into consideration.
The ranges of different performance aspects, i.e., Ipeak, Ivalley, PVCR, Vpeak, and Vvalley (also regarded as the operating voltage VDD) are respectively shown in Fig. 6a-d, which illustrate the overall performance of the Si XTD concept. Since there are four device parameters of variation in the simulations, here, Lgap is used as a basis of categorization, i.e., the horizontal axis. It can be inferred from the figures that Si XTDs with various device parameters have an Ipeak from about 10−10 A μm−1 to 10−8 A μm−1 (equivalent to a current density of 100-102 A cm−2), an Ivalley from about 10−15 A μm−1 to 10−12 A μm−1 (equivalent to a current density of 10−5-10−2 A cm−2), and a VDD roughly from 1.0 V to 1.5 V. The PVCR of Si XTDs could even reach beyond 106.
Fig. 6. Range of performance for Si XTDs with various device parameters. a, Range of values for peak current (Ipeak). b, Range of values for valley current (Ivalley). c, Range of values for peak-to-valley current ratio (PVCR). d, Range of values for drain voltages corresponding to Ipeak and Ivalley (Vpeak and Vvalley). Abbreviations: Si XTD, silicon cross-coupled gated tunneling diode. |
Fig. 7 illustrates all the Si XTDs that could meet our requirements in the simulations, where, every single quadrilateral curve represents one Si XTD with specific device parameters. In addition, the solid curves represent Si XTDs with a PVCR of above 105. As shown in Fig. 7, for the Si XTDs with device parameters within that are used in the simulations (mentioned at the beginning of the subsection), it is often possible to achieve an Ipeak more than 10−10 A μm−1 and a PVCR beyond 103, but a careful selection about the combination of device parameters is required. Furthermore, when device parameters are located within such a range (Lgap = 5-10 nm, d = 3-4 nm, Na = 3.5-5 × 1019 cm−3 and Na = 2.5-4 × 1019 cm−3), it is very likely to obtain Si XTDs with a PVCR over 105. The figure shows that there are reasonable process margins for our Si XTDs. In other words, if some of the device parameters shifts during actual processing, the performance will not be influenced significantly.
Fig. 7. Radar diagram that illustrates the device parameters of all Si XTDs with reasonable performance. Abbreviations: Si XTD, silicon cross-coupled gated tunneling diode. |
SPICE SIMULATION OF TSRAM BASED ON SI XTD
Up till now, simulation results and discussions have demonstrated the great performance and feasibility of the Si XTDs, further, it is natural to become interested in the performance of TSRAM-based on such devices. Therefore, SPICE simulation for it is conducted in this section. In the SPICE simulation, the compact model of the Si XTD is based on the I-V characteristics in Fig. 3b. Here the width of the pn junction is set to 30 nm, thus the peak current and parasitic capacitance of the Si XTD should be 6.18 pA and 2.77 × 10−18 F, respectively. For the transistors, a 55-nm CMOS model is adopted. The operation voltage VDD is set to be 1.38 V.
As is shown in Fig. 8a, a typical TSRAM cell is constructed based on a pair of Si XTD devices in Fig. 3a. For the convenience of simulation, two of transistors are adopted in the simulation instead of one, one of which is employed to control the write circuit on the right side of Fig. 8a, and another is in charge of the readout circuit on the left. Therein, WL and WL_R are signals intended to control the operations of the write and read, respectively. BL denotes the input signal, while BL_R is the signal received directly in the readout circuit. Bit is the signal stored in the bistable memory element based on the two Si XTD devices. And Rdata is the final readout signal processed by the circuit. It should be noted that there is an additional transistor in the readout circuit to set the voltage at BL_R to VDD/2 before it is driven by bit. Subsequently, signals from bit to BL_R can be distinguished between “0” and “1” after being processed by an inverter, and finally the readout signal, Rdata, is obtained. Due to the presence of the inverter, the readout signal Rdata is opposite to that stored in bit, but it could be processed later.
Fig. 8. SPICE simulation for a TSRAM cell based on Si XTD. a, Schematic of the TSRAM cell. b, Results of transient simulation, illustrating write/read function of the TSRAM cell. Abbreviations: Si XTD, silicon cross-coupled gated tunneling diode; TSRAM, tunneling-based static random-access memory. |
The results of the transient simulation are depicted in Fig. 8b. For a comprehensive demonstration of the function of the TSRAM cell, different write and read operations are performed alternately. The operation of writing "0" and "1" is respectively carried out at 15 ns and 35 ns, and correspondingly, "0" and "1" can be read after 20 ns and 40 ns. As shown in Fig. 8b, all these functions can be realized successfully by the TSRAM cell. When the write operation is performed, the signal at bit will become identical to that at BL, i.e. the information from BL will be stored at bit. And when the read operation is performed, the signal at Rdata will become opposite to that at bit (due to the inverter mentioned before), i.e. the information stored at bit is read out after processing. Note that the voltage at bit will change suddenly during the read operations, this could be attributed to the charge sharing between bit and BL_R.
Table 1 shows the performance of the TSRAM based on Si XTD extracted from the simulation, a comparison with the TSRAM based on Si/Ge XTD in ref.38 and a conventional 6T-SRAM was also conducted. As presented in Table 1, the TSRAM based on Si XTD has similar write and read latency to the one based on Si/Ge XTD, which is much better than the performance of 6T-SRAM. Furthermore, the theoretical standby power of the TSRAM based on Si XTD is significantly lower than that of 6T-SRAM, even much lower than that of the TSRAM in ref.38, owing to the ultralow valley current of Si XTD. Therefore, these results have verified the potential of Si XTD devices to achieve TSRAM with great performance and ultralow standby power.
Table 1. Performance comparison of different SRAM cells. |
| Type | Write latency (ps) | Read latency (ps) | Standby power (nW) | Reference |
|---|---|---|---|---|
| TSRAM (Si XTD) | 176 | 189 | 4.21 × 10−3 | - |
| TSRAM (Si/Ge XTD) | 125 | 246 | 0.298 | 38 |
| 6T-SRAM | 448 | 378 | 22 | 43a |
aData of write/read latency for the 6T-SRAM is from ref.38. Si XTD, silicon cross-coupled gated tunneling diode; TSRAM, tunneling-based static random-access memory. |
CONCLUSION
Based on the existing work, this manuscript presents a design of silicon tunneling devices called Si XTD, which is based on a simple, heavily doped Si pn junction with reverse bias applied and a pair of additional gates to control the energy band. As TCAD simulations show, quite significant NDR effect could be observed for this kind of device, of which PVCR may reach beyond 106 with a peak current density of 100 to 102 A cm−2. And further SPICE simulation indicates that such devices are quite suitable to construct ultralow-power TSRAM cells with great performance.
Compared with Esaki TDs and RTDs, Si XTDs not only exhibit much higher PVCR but also have a very simple structure. In addition, since the structure of such devices is quite similar to that of CMOS, Si XTDs are almost completely compatible with the mainstream Si technology, which is easy to implement on silicon or SOI substrate. However, because the gap distance between the gates is quite short and the depth of the doping layer is quite shallow, there will be some challenges for the actual process, and the advanced CMOS process (such as sub-5 nm process and ultra-shallow junction technology) should be adopted. Despite all this, thanks to Si XTDs, silicon-based TSRAM devices with high density, ultralow standby power and manufacturability may be expected to be realized.
MISCELLANEA
Acknowledgments This work was supported by the National Key Research and Development Program of China under Grant No. 2021YFB2800304.
Author contributions Zhenyun Tang: Data curation, Formal analysis, Methodology, Writing - original draft, Writing - review & editing. Zhe Wang: Data curation, Investigation, Methodology. Zhigang Song: Conceptualization, Funding acquisition, Investigation, Project administration, Resources, Supervision. Wanhua Zheng: Funding acquisition, Project administration, Supervision.
Declaration of Competing Interest The authors declare no competing interests.
