INTRODUCTION
In the last 50 years, on-chip power densities have been significantly increased owing to smaller transistors and greater integration1. Following Moore's law, microchip transistors double every two years, going from a few components to over 100 million in the same chip size1. Today, computer central processing units (CPUs) and mobile-phone chips have over 10 billion transistors, and future advancements in chip manufacturing will be likely to increase this number even more2. High integration and high power density make the thermal management issues faced by chips increasingly severe as they operate in high-heat-dissipation environments, limiting their maximum operating frequency and reducing their lifespan2. Besides, high-heat-concentration areas on the surface of a chip, which are known as “hotspots”, can exhibit heat flux values up to five times higher than the chip's average1,3,4. As per another study5, these temperature differences induce thermal stresses within the chip, increasing the risk of damage. Therefore, to satisfy the demands for enhanced chip performance and miniaturization, developing more efficient and practical chip-cooling solutions is highly desired. Traditional active cooling methods, such as fans and liquid cooling, are the primary approaches for computer-chip cooling, however, there are still some limitations. Fans cooling falls short for high-performance chips and can create noise, whereas liquid cooling is costlier, susceptible to coolant leakage, and requires regular maintenance6. Therefore, they are less ideal for portable, quiet and light-weight devices such as laptops and tablets.
Peltier-effect-based thermoelectric coolers (TECs) can directly convert electricity into temperature differences (ΔT), offering advantages such as the absence of moving parts, quick thermal response, silent operation, reliability and scalability. Advancements in semiconductor refrigeration technology have led to the widespread application of TECs, which offer unique advantages over traditional temperature control methods. Microscale TEC (μ-TEC), with its ultra-small size and the ability to be directly integrated onto chips, is particularly valuable for dynamically managing hotspots nearby over short durations7. Fig. 1a illustrates the global demand scale for TEC from 2019 to 2023, along with an estimation for the next five years. Across various industries, the demand for TEC is notably higher in sectors such as “Consumer Electronics” and “Communication” that in other industries, which reaffirms the efficacy and practicality of TEC in temperature control applications. Consequently, during the preceding decade, much effort has been made to develop thermoelectric cooling technology related to chips, as indicated by the surge of publications over the years (Fig. 1b). Generally, the performance of a TEC relies on the thermoelectric properties of the materials and is influenced by the design of the device. Thus, people can select diverse thermoelectric materials and designs to match varying application scenarios and needs, as depicted in Fig. 1c10-18. The cooling capacity of TEC can be evaluated using a coefficient of performance (COP), which could be defined as follows19:
$C O P=\frac{T_{\mathrm{c}}}{T_{\mathrm{h}}-T_{\mathrm{c}}} \times \frac{\sqrt{1+Z T}-T_{\mathrm{h}} / T_{\mathrm{c}}}{\sqrt{1+Z T}+1}$
where, Th and Tc denote the temperatures of the hot side and cold side, respectively. The dimensionless figure of merit ZT measures the thermoelectric performance of materials, determined as ZT = S2σTκ−1, where, S, σ, κ, and T denote the Seebeck coefficient, electrical conductivity, thermal conductivity, and absolute temperature (in Kelvin), respectively. Thus, a specific material with a high ZT value often indicates superior thermoelectric energy conversion efficiency and high COP20. Researchers have strived to improve the thermoelectric cooling technology in the recent years, focusing on materials and device performance21. However, due to limited material capabilities, only bismuth telluride (Bi2Te3) alloys have achieved commercial use in thermoelectric devices (TEDs) operating near room temperature. It is worth noting that, apart from optimizing high ZT thermoelectric materials and thoughtful TEC device design, other factors, such as the contact resistance between the TEC and the heat sink, and internal and surface resistance of the TEC, also play a significant role in the practical refrigeration performance of TECs. Fig. 1d summarizes the cooling temperature difference (ΔT) and COP of Bi2Te3-based thin-film thermoelectric materials over the past 14 years19,22-40. It indicates that the consistently achieved ΔT of around 10 K is comparable to the cooling capacity of current desktop computer CPUs using water cooling systems41,42, which further emphasizes TEC's potential in chip cooling.
Fig. 1. Development of on-chip thermoelectric cooling devices. a, The global market size of Peltier TEC modules8. Reprinted with permission8. b, The increasing trend in the number of publications published with the keywords “thermoelectric” and “chip” since 20009. Reprinted with permission from9. c, Thermoelectric materials, device design, and application of TECs10-18. Reprinted with permission from refs.10-18. © 2009 Macmillan Publishers Limited. © 2013, 2022 The Author(s). © 2018, 2022 Elsevier Ltd. © 2021 IEEE. © 2021 Elsevier Inc. © 2023 Wiley-VCH GmbH. © 2023 Elsevier B.V. d, Cooling performance (ΔT) and coefficient of performance (COP) of TECs based on some typical thermoelectric films19,22-40. Reprinted with permission from refs.19,22-40. © 2010, 2012 American Vacuum Society. © 2010, 2013, 2014, 2018, 2022, 2023 Elsevier Ltd. © 2016 Elsevier Ltd and International Institute of Refrigeration. © 2018, 2019, 2022, 2023 The Author(s). © 2020 Elsevier B.V. © 2022 IEEE. Abbreviation: TEC, thermoelectric cooler. |
TECs are reliable, low-maintenance and scalable, allowing for a modular setup1. As shown in Fig. 2, the cold side is usually affixed to the surface of the chip, whereas the hot side connected to a heat transfer device (such as finned heatsink). As previously mentioned, TEC performance hinges on the material's ZT. Through the optimization of atomic disorder, Roychowdhury et al.43 achieved exceptional thermoelectric performance in AgSbTe2, resulting in a ZT of 1.5 at room temperature and reaching a peak of 2.6 at 573 K. Xu et al.44 developed flexible thermoelectric materials with the adoption of conductive polymers, albeit with lower room-temperature ZT values than high-performance Bi2Te3-based alloys. Nevertheless, the inherent attributes of polymer-based flexible thermoelectric materials, including flexibility, cost-effectiveness and low toxicity, have made them increasingly attractive in the recent years. Hou et al.24 explored Bi0.5Sb1.5Te3/epoxy films for flexible TE modules, achieving a 24% improvement in stable temperature difference under the same applied electrical current, in contrast to prior reports. Hence, developing high-performance TEC thin films is still of paramount importance for the efficient thermal management of high-performance chips45.
Fig. 2. Schematic diagram of the on-chip thermoelectric cooler (TEC). |
In light of advancements in thermoelectric science and technology, TEC has emerged as a promising active cooling solution due to its exceptional performance2,46,47. With the development of high-performance chip and increasing demand for portable electronic devices, active cooling, maily via TEC, holds significant potential as the future mainstream choice. Therefore, it is crucial to provide a timely overview of recent developments in on-chip thermal management utilizing TEC. This review focuses on the fundamental principles, materials, device design, and integration associated with on-chip TECs. Additionally, it outlines the future challenges and prospects in this field. It is expected this comprehensive review will engage researchers, offer valuable insights, and promote the application of TECs in electronics.
THE PRINCIPLES AND DESIGN RULES OF THERMOELECTRIC COOLERS
Since the discovery of the Peltier effect in 1834, researchers have been exploring and developing solid-state cooling devices48. It was not until the mid-1950s that doped semiconductors demonstrated superior thermoelectric performance compared to metals49. Despite decades of researches, TECs remained relatively inefficient, operating at around 10% of the Carnot efficiency50, leading to a slowdown in TEC research. It was not until the early 1990s that theoretical predictions suggested that low-dimensional materials, such as two-dimensional superlattices, could be promising for high-performance thermoelectric materials51. Since then, substantial theoretical and experimental efforts have focused on new materials and designs for high-performance TECs. Starting in 2000, the demand for on-chip hot spot cooling further fueled the exploration of novel TECs. In this section, the principles and design rules for TECs are introduced.
$Q_{\mathrm{c}}=\left(S_{\mathrm{p}}-S_{\mathrm{n}}\right) I T_{\mathrm{c}}-K\left(T_{\mathrm{h}}-T_{\mathrm{c}}\right)-\frac{1}{2} I^{2} R$
where, Sp and Sn denote the Seebeck coefficients for the p-type and n-type thermoelectric legs, and Tc and Th are the temperature at the cold and hot sides of the TEC, respectively. I, K and R correspond to the current, overall thermal conductance, and overall electrical resistance of the unicouple, respectively. K and R can be represented as follows:
$K=\kappa_{\mathrm{p}} \frac{L_{\mathrm{p}}}{A_{\mathrm{p}}}+\kappa_{\mathrm{n}} \frac{L_{\mathrm{n}}}{A_{\mathrm{n}}}$
$R=\rho_{\mathrm{p}} \frac{L_{\mathrm{p}}}{A_{\mathrm{p}}}+\rho_{\mathrm{n}} \frac{L_{\mathrm{n}}}{A_{\mathrm{n}}}$
where, $K$, ρ, L and A represent the thermoelectric unit's thermal conductivity, electrical resistivity, thickness, and cross-section area, respectively. To maximize the Qc, TECs generally require substantial (Sp − Sn) and minimal values for R and K. When applying current to the TEC, it generates a voltage drop that encompasses the resistance voltage across both ends of the thermoelectric component and the Seebeck voltage. Therefore, the power consumption of the TEC is given as follows:
$P=V I=\left(S_{\mathrm{p}}-S_{\mathrm{n}}\right)\left(T_{\mathrm{h}}-T_{\mathrm{c}}\right) I+I^{2} R$
We have introduced the coefficient of performance (COP) for TEC and provided its definition in Eq. (1), which represents the maximum COP value. In general, COP can be obtained by dividing the net cooling power of the cold side by the power consumption of the system.
$\mathrm{COP}=\frac{Q_{\mathrm{c}}}{P}=\frac{\left(S_{\mathrm{p}}-S_{\mathrm{n}}\right) I T_{\mathrm{c}}-K\left(T_{\mathrm{h}}-T_{\mathrm{c}}\right)-\frac{1}{2} I^{2} R}{\left(S_{\mathrm{p}}-S_{\mathrm{n}}\right)\left(T_{\mathrm{h}}-T_{\mathrm{c}}\right) I+I^{2} R}$
Subsequently, the optimal current (Iopt) corresponding to the maximum COP (COPmax) can be found by differentiating the current from Eq. (2) and setting it equal to zero.
$\left(\frac{d Q_{\mathrm{c}}}{d I}\right)_{\mathrm{opt}}=0 \quad \rightarrow \quad I_{\mathrm{opt}}=\frac{\left(S_{\mathrm{p}}-S_{\mathrm{n}}\right) T_{\mathrm{c}}}{R}$
Thus, the cooling power (Qc) reaches its maximum value (Qmax) when I = Iopt.
$Q_{\max }=\frac{\left(S_{\mathrm{p}}-S_{\mathrm{n}}\right)^{2} T_{\mathrm{c}}^{2}}{2 R}-K\left(T_{\mathrm{h}}-T_{\mathrm{c}}\right)$
To determine the maximum cooling temperature that a TEC can achieve, the heat removed from the cold side is set to zero, Qmax = 0, resulting in the maximum temperature difference (ΔTmax) between the cold and hot sides of the TEC.
$\Delta T_{\max }=\frac{\left(S_{\mathrm{p}}-S_{\mathrm{n}}\right)^{2} T_{\mathrm{c}}^{2}}{2 K R}=\frac{Z T_{\mathrm{c}}^{2}}{2}$
It should be noted that in addition to COP, the ΔTmax can also be adopted to measure the cooling performance of TEC, which represents the ability to obtain a lower temperature on the cold side at a given hot-side temperature. For simplicity, it is often assumed that the Seebeck coefficients are equal but opposite in sign (i.e., Sp = −Sn = S) and that thermal conductivity, electrical resistivity, and geometry are equal for both elements (i.e., ρp = ρn = ρ, κp = κn = κ, Lp = Ln = L, Ap = An = A). Thus, the Z in Eq. (9) can be given and simplified as follows:
$Z=\left(\frac{S_{\mathrm{p}}-S_{\mathrm{n}}}{\sqrt{\kappa_{\mathrm{p}} \rho_{\mathrm{p}}}+\sqrt{\kappa_{\mathrm{n}} \rho_{\mathrm{n}}}}\right)^{2}=\frac{S^{2}}{\kappa \rho}$
Thus, it can be observed that the ΔTmax solely depends on the Z and the Tc, with no relation to the TEC's geometry, cross-sectional area or unit thickness. To achieve the high ΔTmax (i.e., lowest temperature), a thermoelectric material with a high figure of merit (Z) is necessary.
To calculate the maximum COP (COPmax), take the derivative of I in Eq. (6) and make it equal to zero.
$\left(\frac{d \mathrm{COP}}{d I}\right)_{\mathrm{opt}}=0 \quad \rightarrow \quad I_{\mathrm{COP}, \mathrm{opt}}=\frac{\left(S_{\mathrm{p}}-S_{\mathrm{n}}\right)\left(T_{\mathrm{h}}-T_{\mathrm{c}}\right)}{R \sqrt{1+Z T}-1}$
When I = ICOP, opt, the COPmax can be obtained as shown in Eq. (1).
In Eq. (1), where ZT is the average ZT between Th and Tc. The calculated curves suggest that achieving a high COP necessitates a small temperature difference (ΔT = Th − Tc) and a high Z value. To get a large COP, the ΔT must be compromised21.
FABRICATION AND PERFORMANCE OF ADVANCED THERMOELECTRIC COOLER MATERIALS
For TEC, a high COP depends on a high Z value. According to Eq. (10), excellent thermoelectric materials should exhibit the highest Seebeck coefficient and conductivity, and the lowest thermal conductivity possible53. Considering that chips in electronic devices such as smartphones and personal computers typically operate in the temperature range of 20 to 100 °C, it is of great significance to develop near-room temperature thermoelectric cooling materials and devices with excellent performance to advance on-chip cooling technology41. High-performance TEC still predominantly utilizes traditional bismuth telluride (Bi2Te3)-based thermoelectric materials renowned for their excellent thermoelectric properties near room temperature50. In this section, overviews on several commonly used thermoelectric materials in on-chip cooling applications are firstly conducted.
Bi2Te3-based alloys
Bi2Te3-based alloys, particularly alloys combining Sb2Te3 (p-type), Bi2Te3 and Bi2Se3 (n-type), are considered to be advanced materials in thermoelectric cooling. The crystal structure of Bi2Te3 is rhombohedral with a space group of R3m (Fig. 3a)54. Spin-orbit coupling induces band inversion, resulting in an indirect band gap of 0.109 eV (Fig. 3b). Fig. 3e shows the corresponding density of states of Bi2Te3 and illustrates the contributions of the element orbits to the valence and conduction bands. The intrinsic Fermi level of Bi2Te3 resides in the middle of the band gap. However, in practical Bi2Te3, introduction of Te vacancies during synthesis may bring the Fermi level closer to the conduction band, which is possibly ascribed to Te evaporation and low formation energy. The low lattice thermal conductivity of Bi2Te3 is attributed to a lower group velocity and increased phonon scattering from the strong coupling between acoustic and optical phonons21. Consequently, researches on Bi2Te3 concentrate on improving its electrical transport properties, specifically optimizing carrier type and concentration62.
Fig. 3. Bi2Te3 and Mg based thermoelectric materials and their cooling performance. a, Unit cell, b, band structure, and c, corresponding density of state of Bi2Te3. Reprinted with permission from ref.54. © 2023 The Authors. d, Crystal structure of the room-temperature α-MgAgSb phase, looking along the <001> and <110> directions. Reprinted with permission from ref.55. © 2012 American Physical Society. e, Comparison of cooling performance and the corresponding hot-side temperature of Te-based, Mg-based, and Te/Mg-based TECs13,56-61. Reproduced with permission from refs.13,56-61. © 2018, 2022 The Royal Society of Chemistry. © 2021 American Association for the Advancement of Science. © 2021 Elsevier Inc. © 2022, 2023 The Author(s). |
Bi2Te3-based alloys and devices are widely used in automobile63, medical64, and aerospace65 applications. They are commonly featured with large-scale commercial solid-state TEDs with a large size of more than 10 per square centimeter66. As implantable/wearable/electronic products evolve, TED designs have been diversified, including miniature and flexible TEDs, and integration into multifunctional devices such as solar cells67. The on-chip TECs are typically made of room-temperature thermoelectric materials. Bi2Te3-based thermoelectric materials remain the preferred choice for commercial TECs due to their ZT exceeding 0.7 at temperatures below 350 K, with a high ΔTmax of 60 to 70 K2,68.
Mg-based alloys
While Bi2Te3-based thermoelectric materials excel near room temperature, the scarce availability of tellurium (Te) (<0.001 ppm) presents a potential hindrance to its widespread commercial applications. Recently, magnesium (Mg)-based compounds, such as p-type α-MgAgSb and n-type Mg3Sb2-xBix, have emerged as promising options, delivering comparable performance to Bi2Te3-based alloys at or near room temperature59. Mg, which ranks the eighth in earth's abundance at ∼29,000 ppm, surpasses Te in availability and offers a more cost-effective solution. Hence, Mg-based thermoelectric materials exhibit promising prospects for research and practical applications.
The crystal structure of typical α-MgAgSb is a distorted Mg-Sb rock-salt sublattice rotated by 45° along the c-axis (Fig. 3d)55. With increasing temperature, there is an observed trend of increased structural symmetry. Fig. 3e illustrates the maximum cooling temperature difference (ΔTmax) and the corresponding hot-side temperature for Bi2Te3-based, Mg-based, and devices composed of both in thermoelectric cooling applications13,56-61. Currently, the ΔTmax of Te-free Mg-based TEDs can rival commercial Bi2Te3-based counterparts, further substantiating the significant potential of Mg-based thermoelectric materials in large-scale commercial refrigeration.
Ag2Se-based alloys
Ag2Se-based materials are typical n-type semiconductors with a narrow bandgap, which exists in two phases: the low-temperature α-Ag2Se phase (orthorhombic) and the high-temperature β-Ag2Se phase (cubic). The phase transition temperature is around 406 K69,70. The β-Ag2Se phase exhibits semiconducting properties due to a narrow bandgap (0.15 eV), whereas the α-Ag2Se phase displays metallic superionic properties, in which Ag+ ions become mobile within a rigid sublattice of Se2-71,72. In recent years, Ag2Se has garnered widespread attention in researches due to its high mobility μ, moderate Seebeck coefficient S, and relatively low lattice thermal conductivity κL. The average ZT value of Ag2Se at room temperature reaches 0.7, indicating its significant potential in the fields of room-temperature power generation and refrigeration69,73,74. As currently reported, Ag2Se exhibits a maximum ZT value of 1.2 at 390 K75-77, which is comparable to that of Bi2Te3-based thermoelectric materials. These excellent thermoelectric performances of Ag2Se make it a promising candidate to be used as a flexible thermoelectric films69 like organic/Ag2Se hybrid film78-80, inorganic/Ag2Se hybrid films81-83, stoichiometric ratio-manipulated Ag2Se film84-86 and printed Ag2Se87-89.
Micro bulk and thin films, characterized by smaller cross-sectional areas and shorter lengths of thermoelectric legs, offer advantages for integration into portable devices and serve as primary TECs for on-chip cooling2. In addition to the three categories mentioned earlier, several new materials are available for micro-bulk and thin-film TECs, including carbon-based materials such as graphene sponges90,91, oxides such as Al0.02Zn0.98O/Ca3Co4O992, zintls-containing compounds such as Cu0.9Ni0.1AgSe93, CsBi4Te694, Mg3BixSb2−x95 and superlattice materials.
Fundamental to optimizing thermoelectric cooler materials performance
To enhance the TEC cooling performance, it is crucial to use thermoelectric materials with high ZT values and suitable device design96,97. Exceptional thermoelectric materials demonstrate heightened cooling capabilities, and effective device design is essential for maximizing their cooling potential12. As mentioned earlier, an ideal thermoelectric material should possess the highest possible Seebeck coefficient and conductivity as well as the lowest possible thermal conductivity, as Slack proposed the “phonon-glass electron-crystal’’ concept21. Insulators have very low conductivity, whereas metals have low Seebeck coefficients and high thermal conductivity. So far, the best-performing thermoelectric materials have been found in heavily doped semiconductors. In addition, according to the Wiedemann-Franz law, the thermal conductivity of metal materials dominated by electrons is proportional to their conductivity61. Therefore, it is difficult to suppress the thermal conductivity of metal materials while improving their conductivity. In semiconductors, thermal conductivity is established by the flow of electrons and phonons, but most heat transfer is attributed to phonons. A common method to reduce phonon thermal conductivity is through alloying or doping, since mass difference scattering in alloys or doped semiconductors can significantly reduce lattice thermal conductivity without significantly weakening conductivity, thereby improving thermoelectric performance.
Improving the electrical transport properties of materials is also essential for optimizing the thermoelectric performance21, involving enhancements in carrier mobility and band engineering. Carrier mobility is significantly affected by carrier concentration, scattering and effective mass (m∗). Strategies to enhance mobility mainly include single-crystal growth, texture engineering, defect control, crystal symmetry modification and band sharpening. The effective mass is a crucial parameter influencing electrical transport, particularly the Seebeck coefficient, primarily determined by the electronic band structure. Strategies for modifying the band structure involve introducing resonant energy levels to increase states density near the Fermi level and aggregating multiple bands to activate more charge carriers, facilitating hole injection into electronic transport.
Thermoelectric performance optimization is often linked to the material type. For example, layered Bi2Te3-based materials inherently exhibit low thermal conductivity, such materials emphasize improving their electrical transport properties. Additionally, optimization strategies for thermoelectric performance vary between thin films and bulk materials. Strategies applicable to different TEC systems may also vary. Detailed descriptions regarding these aspects can be found in other articles98. The discovery of novel strategies is desired in the future researches to further enhance the cooling performance of TECs.
Fabrication and performance of thermoelectric cooler materials
The preparation methods for bulk thermoelectric materials mainly include zone melting, Bridgman method and mechanical alloying. The preparation methods of thin-film thermoelectric materials include physical vapor deposition, chemical vapor deposition, magnetron sputtering, electrochemical deposition (ECD), atomic layer deposition and molecular beam epitaxy. These methods offer diverse options for preparing thin-film TEC devices based on the properties of the material. As shown in Fig. 4a, high-performance Bi2Te3 films with staggered layer could be prepared by peeling along the (000l) crystal plane of Bi2Te3 single crystals99. The room-temperature power factors for the resulting p- and n-type Bi2Te3 films are 4.2 and 4.6 mW m−1 K−2, respectively. This composite preparation method introduces a novel approach for designing high-performance wearable TEDs or TEC. Fig. 4b depicts a p-type Bi0.5Sb1.5Te3 film prepared by magnetron sputtering100. Through synergistic texture formation and Bi/Sb-Te antisite doping, a room-temperature power factor of 4.53 mW m−1 K−2 and a ZT value of 1.5 were achieved, accompanied by a high mobility of 100 cm2 V−1 s−1. Fig. 4c illustrates the schematic diagram of high-crystallinity MnTe-Sb2Te3 superlattice-like thermoelectric films prepared by molecular beam epitaxy (MBE)101. By modulating interface charge transfer, the superlattice film attained high carrier concentration, carrier mobility, Seebeck coefficient, and a power factor of 2.79 mW m−1 K−2 at 381 K. Similarly, Bulman et al. reported thermoelectric properties resembling those of superlattice materials47, but with a lower in-plane power factor, resulting in a significantly lower ZT of 1.4 at 300 K. Therefore, utilizing of superlattice thin films to enhance ZT values remains controversial and debatable102.
Fig. 4. Bi2Te3 based thin films with different structures. a, Schematic diagram illustrating the staggered-layer structure in a flexible BST-film, a model diagram and corresponding simulated STEM images depicting the interlayered structures in the BST thin film. Reprinted with permission from ref.99. © 2023 The Author(s). b, Schematic diagram illustrating the fabrication process of a BST-based thermoelectric thin film using magnetron sputtering method100. c, The structure and the growth recipe of the SLs and QD-SLs101. Reprinted with permission from refs.100,101. © 2021, 2022 Wiley-VCH Verlag. Abbreviations: BST, Bi0.5Sb1.5Te3; QD-SL, Quantum dot-Superlattice; SL, Superlattices; STEM, Scanning Transmission Electron Microscopy. |
APPLICATION OF INTEGRATED ON-CHIP THERMOELECTRIC COOLER
Microscale TECs (μ-TECs) have dimensions in the range of micrometers or nanometers2,103. They exhibit a traditional vertical layered structure known for its lower electrical resistance when compared to thin-film structures. The challenge in manufacturing μ-TECs lies in the intricate bonding of thermoelectric legs and electrodes due to their reduced dimensions. Various techniques have been developed to address this issue, including electroplating104, flip-chip technology105, complementary metal-oxide semiconductor106, ECD107, and photolithography104.
Significant strides have been made in the field of μ-TECs in recent years. Fig. 5a illustrates the fabrication of advanced μ-TEC devices through a combination of standard photolithography and modified ECD techniques108. The μ-TEC comprises four vertical layers: substrate, bottom contact, thermoelectric elements, and top bridging contact. The fabrication process involves multiple steps, including photolithography and mask alignment. Starting with a silicon substrate topped with a 100-nm-thick insulating Si3N4 layer, successive layers of Cr and Au are deposited as a conductive seed crystal layer. An ECD-Au layer serves as the bottom electrode for the thermoelectric elements. n-type (Bi2(Te0.95Se0.05)3 or BiTeSe) and p-type (pure Te) materials are sequentially deposited using ECD108. After deposition, a 1-μm-thick Au layer is immediately electroplated on top of each thermoelectric leg to prevent oxidation and minimize resistivity. Fig. 5b provides a clear overview of the μ-TEC, highlighting each thermoelectric leg and its interconnections108. Fig 5c displays the local, top, and side views of the μ-TEC, with n-type legs measuring 30 μm in width and 40 μm in length, and p-type legs having a square dimension of 30 × 30 μm2. In a 2 × 2 mm2 substrate area, 220 pairs of legs are integrated, achieving a packaging density of 5500 pairs/cm2, with a filling factor of approximately 20%108. The μ-TEC, vertically independent on the substrate, resembles commercial bulk Peltier coolers. In different current scenarios, characterized by charge-coupled device thermal reflectance microscopy in Fig. 5d, the μ-TEC's cooling performance is elucidated108. Under ambient conditions, applying a small 4-mA current to the integrated μ-TEC shows minimal cooling. In comparison, at 21 mA, a noticeable cooling effect with an ΔT of approximately −4 K is observed. Conversely, reversing the current polarity results in significant heating of the thermoelectric legs with a ΔT of about 3 K. Fig. 5e depicts the cooling dependence on applied current and the transient cooling response of the μ-TEC108. With increasing current from 5 to 140 mA, the net cooling of two thermoelectric pairs tends to gradually increase to a peak of 6 K at around 100 mA and then decrease with further current increments. The typical dependence reveals two competing mechanisms within the μ-TEC: charge carriers contributing to Peltier cooling and Joule heating, with the latter becoming prominent beyond 100 mA and impacting overall cooling performance108. A promising application for μ-TECs is their integration with on-chip cooling or thermal stabilization of devices requiring precise temperature control, such as active photon components in integrated optoelectronic devices108. Fig. 5f illustrates the cooling performance of μ-TEC at varying substrate temperatures108. Measurements at a constant current (70 mA) in ambient conditions maintained the basic temperature within 290 to 380 K with the adoption of commercial Peltier elements. The results show a substantial increase in net cooling with higher substrate temperatures, reaching 12 K at 380 K. This enhancement is attributed to the improved overall thermoelectric performance of the BiTe compound within the measured temperature range109, resulting in elevated cooling power108.
Fig. 5. Micro thermoelectric cooling devices and on-chip heat dissipation performance. a, Schematic fabrication process for integrating the four layers of μ-TEC108; Corresponding b, overview. c, top and side views of the μ-TEC108. d, Optical microscopy image of the integrated μ-TEC device and thermoreflectance images with applied electric currents of 4, 21, and −21 mA108. e, Experimental and simulated net-cooling temperature of two leg pairs in the electric current range 5∼140 mA at room temperature ∼20 °C. Inset: optical and thermoreflectance images with an applied electric current of 70 mA108. f, Stage temperature dependent cooling performance of two in-series-connected μ-TECs in an ambient environment with an applied electric current of 70 mA. Top inset: photograph of the μ-TEC sample mounted on a commercial Peltier element. Bottom inset: thermoreflectance image of two leg pairs at 380 K108. g, Test geometry for the thin-film TEC12. h, Cooling performance of the thin-film TEC12. Reprinted with permission from refs.12,108. © 2009 Macmillan Publishers Limited. © 2018 The Author(s). Abbreviation: μ-TEC, microscale thermoelectric cooler. |
Some electronic110 and bioanalytical111 devices are crucial for targeted and on-demand cooling12. Current solutions often involve bulky or excessively designed system-level approaches12. Micro-TEDs offer a streamlined and energy-efficient solution to these challenges. Fig. 5g illustrates the integration of TEC, which is fabricated using nanostructured Bi2Te3-based thin-film superlattices, into cutting-edge electronic packaging12. These coolers are manufactured on a copper-integrated heat sink, a widely adopted method for cooling silicon microprocessors to enhance heat dissipation and protect chips from mechanical damage12. Fig. 5h illustrates the temperature of the localized high-heat-flux region on the chip as a function of current through the TEC12. Without the TEC, the temperature in the locally heated area is 124.5 °C. When the cooler is connected to the heat sink but not powered, the temperature decreases to 116.9 °C, resulting in a net passive cooling of 7.68 °C. At 3-A current, the device achieves a maximum on-demand (active) cooling of 7.38 °C, and with the aid of the TEC, the overall local cooling effect reaches 14.9 °C. Compared to electrical contact resistance, model predictions highlight the significant role of thermal contact resistance in reducing the performance of the cooler12.
Generally, the passive and active cooling efficiency of TECs is influenced by the design parameters such as leg height, filling ratio, electrode height, gap distance, hotspot size and hotspot heat flux38. Fig. 6a illustrates a schematic diagram of a three-dimensional electronic package with integrated thin-film TEC (TFTEC)38. A silicon carbide (SiC) chip with dimensions of 10 × 10 × 0.4 mm3 is connected to the integrated heat spreader (IHS) via thermal interface material (TIM). The TFTEC, which is embedded in TIM, is directly connected to IHS to enhance heat dissipation112. The IHS has outer dimensions of 30 × 30 × 1.5 mm3, with a dielectric layer coated between TFTEC and IHS. The hotspot region is located at the center of the chip to simulate varying hotspot heat-flux densities38. TFTEC consists of several pairs of TE elements connected in series electrically and in parallel thermally. Each pair comprises one p-type leg and one n-type leg. The area of TFTEC is fixed at 2 × 2 mm3, utilizing Bi2Te3/Sb2Te3 superlattice materials with excellent thermoelectric properties12, as detailed in ref.39. Simulation results in Fig. 6b, analyzed based on Taguchi-Grey method38, elucidate the optimal design factors for maximizing cooling effectiveness. Under these design factors, the passive cooling of 16.82 °C and the maximum active cooling of 12.29 °C are achived by the TEC achieves, leading to a total localized cooling of 29.11 °C for a chip hotspot38.
Fig. 6. On-chip cooling devices and heat dissipation performance. a, Schematic of the 3D electronic package with integrated TFTEC38. b, Hotspot cooling performance of the integrated TFTEC38. Reprinted with permission from ref.38. © 2022 Elsevier Ltd. c, Fabrication process of chip-on-TEC for high-power LED packaging10. d, Thermal infrared images of the cold-side surface of TEC at the input current of 0.5, 1.0, 1.5, and 2.0 A10. e, Physical diagram of chip-on-TEC and cross-sectional heat distribution diagram when applying a 1.0-A current10. f, Cold-side temperature and voltage of TEC under different input currents10. g, Maximum temperature of LED package with chip-on-TEC at the chip current of 1.0 A10. Reprinted with permission from ref.10. © 2021 IEEE. Abbreviations: LED, light-emitting diode; TEC, thermoelectric cooler; TFTEC, thin-film thermoelectric cooler; 3D, three-dimensional. |
TECs also demonstrate promising applications in light-emitting diode (LED) chip thermal management10. Fig. 6c outlines the fabrication process for a high-power LED chip-on-TEC assembly10. The ceramic substrate with patterned copper layers is prepared with the adoption of the Direct Plating Copper technique, serving as the TEC's cold-side and hot-side substrates. Thermoelectric elements, sized 1 × 1 × 2 mm3 for p-type (Bi0.5Sb1.5Te3) and n-type (Bi2Te2.7Se0.3), are aligned and soldered onto the substrate10. A circuit layer composed of Ti/Cu/Ni/Au is applied to the TEC's cold-side ceramic substrate, and four LED chips were aligned and attached to the substrate by the reflowing process. The TEC actively cools the LED chips, as evidenced by thermal images in Fig. 6d, showcasing decreasing cold-side temperatures (4.0 °C, −7.9 °C, −19.9 °C, and −25.8 °C) with increasing input currents (0.5 A, 1.0 A, 1.5 A, and 2.0 A)10. Fig. 6e displays the chip-on-TEC assembly's physical setup and the cross-sectional thermal distribution when applying a current of 1.0 A10. With active cooling by the TEC, the chip temperature is decreased by 94 °C at a current of 1.0 A. Fig. 6f depicts the cold-side temperature and voltage of the TEC under different input currents10. The cold-side temperature of the TEC decreases with an increasing input current. With increasing input current, the heat generated by the Joule effect offsets the heat absorbed on the cold side, resulting in no significant reduction in the cold-side temperature at an input current of 2.5 A. When the current increases from 0.5 to 2.5 A, the TEC voltage linearly increases from 0.7 to 3.1 V. Fig. 6g illustrates the highest temperature on the TEC-integrated chip under various chip currents with the TEC on/off at an input current of 1.5 A10. At different chip currents, the TEC-on chip temperature is significantly lower than the TEC-off chip temperature. At a chip current of 1.0 A, the TEC reduces the chip temperature from 232 to 114 °C. This experimental result, consistent with thermal simulation results, indicates that TEC chips offer a simple and effective active cooling method for the thermal self-management of high-power LEDs10.
Processors are typically partitioned into distinct functional zones, generating varying local hotspot temperatures. Therefore, on-demand cooling is essential to maximize processor performance, particularly in advanced technologies where local hotspots vary during operation113. Consequently, TEC arrays can be fully integrated into commercial multi-core mobile chips to fully leverage their cooling capabilities. Fig. 7a illustrates the planar layout of a specific mobile chip113, indicating each functional component's precise location and names. Fig. 7b displays the corresponding hotspot temperatures on different cores at various time points113. Fig. 7c compares the temperatures captured by an infrared camera with those from a transient thermal Multiphysics simulation model. The high correspondence between actual and simulated temperatures indicates the accuracy of the simulation model113. Fig. 7d shows the temperature reduction of Core0 with and without TEC usage113. This result suggests an approximate 1-°C reduction in the average temperature of Core0. Moreover, when the array functions as a TEG, the harvested energy can compensate for approximately 89% of the power demand113. These findings underscore the potential of self-cooling designs and on-demand systems as prime candidates for addressing hotspot issues and achieving sustainable thermal management2.
Fig. 7. On-demand mobile CPU cooling with thin-film thermoelectric array. a, Diagram of the tested mobile chip used in the simulation, along with the positions and names of each block113. b, Illustration of the chip temperature during the thermal analysis at various points of time113. c, Comparison of the temperature from the IR camera and transient thermal Multiphysics simulation model113. d, Comparison of the temperature of core0 with and without TEC113. Reprinted with permission from ref.113. © 2021 IEEE. Abbreviations: CPU, computer central processing unit. |
In order to meet the increasing demand for chip computational capabilities driven by the recent resurgence of machine learning, tensor-processing units (TPUs) have gained popularity due to their higher power consumption and throughput efficiency than those of graphics processing units (GPUs)114. However, this popularity has led to the emergence of excessive local hotspots114. Elevated chip temperatures may accelerate aging defects, posing a threat to the reliability of semiconductor devices and significantly shortening their lifespan114. Fig. 8a presents a finite element simulation model of a TPU, where a TEC is directly mounted on the top of the TPU die without any TIMs114. Fig. 8b illustrates the inferred thermal map of the TPU die featuring an inactive array of mounted TEC. Despite the superlattice TEC being powered off, the hotspot temperature has been decreased by 10 °C, which is attributed to passive cooling114. Fig. 8c displays the thermal image of a TPU die with the installed TEC under a 5-A current114. The results indicate that the hotspot temperature on the TPU can be reduced from 116 °C to 82 °C when applying the TECs114. These findings suggest that TECs may be indispensable when traditional convective air cooling is insufficient.
Fig. 8. Modeling TPU thermal maps under superlattice thermoelectric cooling. a, A schematic diagram of the finite element simulation model of TPU and a close-up diagram of the superlattice TEC installed on the top of TPU114. b, Thermal map of the baseline TPU die114. c, Thermal of TPU core with integrated superlattice TEC at a current of 5 A114. Reprinted with permission from ref.114. © 2022 IEEE. Abbreviations: TEC, thermoelectric cooler; TPU, tensor-processing unit. |
CONCLUSIONS AND FUTURE OUTLOOK
In recent years, continuous researches on TEC have affirmed its significant potential in on-chip cooling. μ-TECs and TFTECs can be integrated into electronic devices, providing continuous or transient temperature cooling based on chip packaging. The development of 5G technology has increased the density of chip integration and put forward higher requirements for the cooling performance of TEC. Material, structure, and device design are key factors that could influence the TEC performance. Exploring new optimization methods and discovering near-room-temperature refrigeration materials are crucial for enhancing the TEC performance. μ-TECs and TFTECs are the primary on-chip refrigeration devices, but challenges persist in fabrication and optimization due to their small size. Two major challenges that need to be addressed are reducing the contact resistance between TEC and electrodes and minimizing Joule heating to the greatest extent possible. Besides, researches on self-cooling designs and on-demand cooling systems for TECs are also limited, with many still in simulation stages. Thus, developing new TEC materials, optimizing refrigeration, and designing TEC devices are primary research directions for on-chip TECs in the future.
MISCELLANEA
Acknowledgments This work was supported by the National Natural Science Foundation of China (Grant No. 92163211 and 52002137), the Fundamental Research Funds for the Central Universities (Grant No. 2021XXJS008).
Declaration of competing interest The authors declare no competing interests.
