INTRODUCTION
With the development of Internet of Things (IoT) technology, there has been an increasing demand for memory performance, especially in terms of flexible functionality, fast operating speeds, small size, and large storage capacity1-4. Generally, memory devices can be divided into two categories, namely volatile and non-volatile memory. Volatile memory is characterized by data loss in case of a power failure and endowed with the advantage of very fast write and read times. Dynamic random-access memory (DRAM) and static random-access memory (SRAM) are the most two common types of volatile memory5,6. Although non-volatile memory is slower to write and read, it has been widely investigated on its ability to store stable data for long periods after a power failure, among which flash memory is the most mature non-volatile memory technology7,8. NOR flash memory and NAND flash memory are commonly used in flash memory devices9,10, and FG is their basic structure, which is achieved by introducing a FG layer in a metal-oxide-semiconductor field-effect transistor (MOSFET) to achieve reliable endurance and excellent charge retention performance of the FG memory11-13.
The storage action of the floating gate (FG) memory is achieved by trapping and de-trapping charge carriers in the FG layer. During "program"("write") and "erase" operations, the charge is driven through the dielectric layer, while the capture and release of the charge is accomplished by the FG layer, and the captured charge does not disappear even without external energy, thus enabling nonvolatile behavior14,15. In the "program" state, the charge stored in the FG is trapped in a potential well, which shields the vertical electric field between the control gate and the channel layer, resulting in a Vth offset. Obtaining a wide range of adjustable Vth is the basis for building integrated circuits and implementing logic functions16. However, as semiconductor technology nodes continue to shrink with the demand for high data storage density, many unavoidable problems have emerged for MOSFET structured flash memories, such as reduced tunneling oxide thickness leading to charge leakage, reduced FG volume leading to less storage charge, and short channel effects which cannot be addressed well11,17-21. Therefore, there is an urgent need to find new ways to address the limitations of silicon-based flash memory near the physical limit.
One option is to find new materials to break the physical limit of device scaling. The researchers in this community paid their attention to ultrathin vdW materials, which are featured with unique properties such as atomic thickness22,23, absence of dangling bonds24, ultra-high mechanical strength25, as well as high mobility at room temperature26-28. Moreover, vdW materials can be synthesized by mechanical exfoliation, chemical vapor deposition and other methods29-31 and they have emerged as excellent candidates for device manufacturing due to their inherent resistance to short-channel effect and excellent gate coupling at the nanoscale. For example, the simulation study shows that the carrier mobility of graphene can reach up to 44000 cm2 V−1 S−1 even when the carrier density is around 1011 cm−2 32. Hexagonal boron nitride (h-BN) is often used as a high-quality insulating dielectric owing to its large band gap of more than 5 eV33-35. Consequently, the unique atomic thickness, excellent optoelectronic properties, and 3D stackable capacity of vdW materials offer a variety of possibilities for device fabrication36-41. Different vdW materials can be stacked together according to energy band engineering, and vdW heterostructures can be designed flexibly42-46. Bertolazzi et al.47 proposed a device with FG structure built entirely from vdW materials as a nonvolatile memory cell, where the effect of capacitive interference is significantly reduced through reducing the thickness of the FG layers, while graphene is used as the electrode to form ohmic contact. A broad combination of raw materials often exhibits exceptional properties, and vdW structures have been widely utilized in various electronic and optoelectronic applications due to their advantages of simple operation, low cost, and the limitation of overcoming lattice mismatch28,48-55. For example, Liu et al.42 achieved an ultra-fast program/erase speed of 20 ns by designing a suitable potential barrier height and gate coupling ratio for the vdW heterostructure. Similarly, stacking a wide variety of heterojunctions can also display fascinating optical properties. Wang et al.56 found negative photoconductance in ReS2/h-BN/MoS2 vdW-based heterostructures which are rarely observed in vdW heterostructures, and light intensity controlled negative photoconductance also shows potential in implementing optically tunable multi-bit memory devices. The vast library of vdW materials provides strong support for the diverse properties of stacked heterostructures.
Another option is to find new computing architecture, due to the von Neumann bottleneck of inefficiency resulting from the separation of storage units and computing units in conventional computer architectures, the simulation of human brain-like synaptic functions, as well as the implementation of neuromorphic computation through the use of electronic devices tends to be an effective solution57-63. So far, a variety of devices have been widely investigated to achieve synaptic dynamics. Among them, the advantages of two-terminal devices are simple structure, high integration density and low energy consumption53. However, the unpredictability of the formation of conductive filaments will lead to the low reliability of the memristors, moreover, the two-state resistance level also limits its applications. Due to the single tunable conducting channel between two electrodes, the learning function and signal transmission process cannot be realized simultaneously, which is also an existing problem. While the three-terminal FG memory device can solve this problem by separating the paths for writing and reading. Moreover, due to the charge storage role of an additional FG layer surrounded by a dielectric layer, the source/drain channel conductivity can be non-volatile modulated by multi-modal signal64. The synaptic weight could be reflected in the multi-conductivity level of the device, and its advantages also include good thermal stability, reliable cycle endurance, low noise and low power consumption of reading. Compared with two-terminal devices, the three-terminal FG memory could modulate the amount of charge trapped in the FG layer through the charge tunneling process, effectively control the variation range of linearity and update weights, and tend to be a promising candidate for simulating synaptic function65-67.
Compared with traditional FG transistors, vdW material-based FG transistors are more sensitive to external stimulation due to their atomic thickness and reduced shielding effect, and exhibit unique advantages in operating voltage and energy consumption for neuromorphic computing. Some key parameters in different FG synaptic devices are summarized in Table 1. Since its introduction, many novel structures have emerged for FG devices based on vdW materials, and their superior performance is suitable for many applications (Fig. 1). They are expected to develop novel neuromorphic computing system based on FG structure with low power consumption, high parallelism, as well as autonomous learning and decision making68.
Table 1. Comparison between vdW material-based FG transistors and traditional FG transistors. |
| Empty Cell | Material | Endurance (cycles) | Retention time | Operation voltage Vset/Vrset | Energy consumption per spikes | STP/STD/LTP/LTDa | Refs. |
|---|---|---|---|---|---|---|---|
| VdW material-based FG transistors | MoS2/h-BN/Gr | ∼105 | - | −4 V/+3 V | ∼5 fJ | STP/LTP | 69 |
| MoS2/h-BN/Gr | >105 | >104 s | ±10 V ∼ ±13 V | ∼18 fJ | LTP/LTD | 70 | |
| MoS2/h-BN/Gr | >103 | >103 s | +10 V/−8 V | ∼28 pJ | STP/LTP | 71 | |
| BP/Al2O3/BP | - | - | ±5 V | sub-fJ | LTP | 72 | |
| Empty Cell | HfS2/h-BN/Gr | >103 | >104 s | −20 V/+15 V | 0.2 pJ | STP/LTP/LTD | 73 |
| Traditional FG transistors | ZnO/Al2O3/ZnO | 10000 | 30000 s | +18 V/−15 V | - | - | 74 |
| Empty Cell | silicon/oxygen/metal | - | - | +10 V/−7 V | - | STP/LTP/LTD | 64 |
| Empty Cell | IGZOb/SiO2/Au-NCSc | 1050 | - | ±35 V | - | - | 75 |
| Empty Cell | silicon/oxygen/nitrogen | - | - | −11 V /+10 V | - | - | 76 |
ashort-term potentiation/short-term depression/long-term potentiation/long-term depression bindium-gallium-zinc-oxide cAu-nanocrystals |
Fig. 1. History of the development of FG device. |
In this review, the focus was on memristor devices with FG structures using vdW materials, combining the advantages of vdW materials with heterojunctions that make vdW materials-based FG structures more worthy to be investigated. The working principles and typical structures of the FG will be introduced firstly, with a focus on FG memristors modulated by different stimuli, their applications in neuromorphic computing were introduced subsequently. Finally, the problems existing today were summarized and some possible solutions were put forward.
WORKING PRINCIPLES OF FG DEVICE
The FG structure is characterized by a FG layer surrounded by the insulating dielectric layer. When applying the gate bias, the charge carriers are injected from the semiconductor channel and stored in the FG, which is called the “program” operation. When applying the reverse gate bias, the carriers captured in FG return to the channel, which is called the “erase” operation. For the capture and de-capture process, the charge carrier must be transferred from the FG or into the FG according to several main mechanisms, such as the hot-electron injection mechanism, Fowler-Nordheim (F-N) tunneling mechanism, and direct tunneling mechanism77.
Hot-electron injection describes the current generated by highly energetic electrons overcoming the energy barrier78. When a large lateral electric field is applied between the source and drain electrodes, electrons absorb enough energy to possess the ability to “jump over” the energy barrier. Under the action of the vertical electric field induced by the gate, the electrons can be captured by the FG layer. This mechanism permits ultra-fast write speeds and lower gate voltages. However, irregular injection of electrons may result in useless “program” operations and increase power consumption. Different from the hot-electron injection, F-N tunneling is a high-field-assisted tunneling mechanism in which electrons can pass through the thin barrier under a high electric field79-83. The physical mechanism of F-N tunneling is divided into two parts, where electrons are thermally excited to a higher energy level firstly, and subsequently reach the FG through a triangular barrier. With F-N tunneling, lower power consumption and high carrier tunneling efficiency can be achieved. Nonetheless, it also possesses certain drawbacks, such as the requirement for a highly applied electric field and long access time. For high electric fields and sufficiently thin tunneling dielectrics, charge carriers can pass directly through the dielectric layer, where direct tunneling dominates84. Compared with the F-N tunneling mechanism, it is endowed with the advantage of fast programming speed. However, the data retention characteristics will be affected due to the smaller dielectric thickness. Also, the direct tunneling current is affected by many factors (such as the external electric field), which is more complicated than the F-N tunneling mechanism.
TYPICAL STRUCTURES OF FG DEVICE
The vdW material-based memory with a FG structure consists of a channel layer, a blocking dielectric layer, a tunneling dielectric layer, and a FG layer sandwiched between the two dielectric layers.
In FG memory device, the conductance of the channel can be effectively modulated by the charge stored in the FG layer and the gate voltage. The conductance level of the channel hints at the possibility of multi-bit storage. VdW materials are often used as channel materials owing to their advantageous properties such as high carrier mobility, large bandgaps, and various physical phenomena, allowing different ON and OFF states to be easily achieved56,85,86. Min et al.87 demonstrated the full vdW stacking devices with device structure of graphene-channel/MoS2-FG and MoS2-channel/graphene-FG, respectively. By changing the stacking order and thickness of materials, the hysteresis and conductance polarity of the transistor are successfully controlled. Li et al.88 obtained a large memory window of up to 60 V at a control gate voltage of 40 V by using bipolar black phosphorus as the channel material. Wu et al.89 successfully implemented direction-sensitive multilevel memory devices using the anisotropy of the ReS2 material as the channel material, which yields surprising results by exploiting the properties of different channel materials.
A thicker blocking layer and a thinner tunneling layer exist in a FG memory device structure. The thicker blocking dielectric layer can effectively prevent carrier transfer to the gate electrode during the program and erase operations with applied voltage. Recently, Li et al.90 replaced the blocking dielectric layer in conventional FG memories with a threshold switching layer, graphdiyne oxide, which allows charge injection from the control gate to the FG layer directly, resulting in ultra-high operating speed (20 ns), low operating voltage (2 V), and long retention time (10 years). The relatively thin tunneling dielectric layer would be sufficient to prevent the charge stored in the FG from returning to the channel when no power supply is available after the tunneling task, thus facilitating the operation of the non-volatile memory. For the limited erase/write endurance of FG transistors used for synapses, several normal methods are normally adopted to solve this issue, like thinning the FG layer, reducing the charge of the FG charging and controlling the temperature of the device91, etc. In addition, Moon et al.92 have summarized several studies and showed that, vdW materials such as h-BN, tend to show superior breakdown strength and unprecedented reliability even with a sub-nanometer thickness when compared with conventional dielectrics, which implies that vdW material is conducive to good erase/write endurance as a tunneling dielectric compared with traditional oxides. Many FG transistors with the usage of h-BN as the tunnel dielectric have achieved write/erase endurance of up to ∼105 cycles69,93,94 or higher value. Besides the common dielectric materials like h-BN95, HfO296,97, Al2O398, etc, Xiong et al.99 naturally oxidized vdW semiconductor BP to form a phosphorus oxide (POx) layer, which exhibits good insulating properties with a clean interface. Such a dielectric layer grown directly on the semiconductor surface100,101 helps to form a key functional charge-trapping layer with superior performance.
In FG memory device, information is converted to charge storage level and stored in FG. Therefore, the FG material determines the performance of the memory to some extent. However, the interference between adjacent cells will lead to threshold voltage changes and affect the programming speed of the device. Lee et al.102, through the simulation of formula (The floating gate interference coupling ratio, γfg, is defined as where CFG denotes parasitic capacitors surrounding the floating gate CFGX, CFGY, or CFGCG, and CONO is the control gate to floating gate capacitance), found that the reduction of FG thickness can significantly reduce interference, which also confirms that it is a good option to prepare FG by using vdW materials87,103,104. Graphene is a very popular floating gate material owing to its Dirac cone-shaped zero-gap bands, which enables the continuous filling of ambipolar carriers (i.e., electrons and holes) and produces an outstanding charge storage function105-108. The exploration of other FG materials continues to improve charge storage efficiency109-115. Kim et al.116 investigated the properties of gold nanoparticles (AuNPs) as FG materials with controllable charge trap density, excellent chemical stability, high work function, and effective charge limitation, indicating the great potential of introducing AuNPs as FG materials in vdW material-based FG devices. Gong et al.117 adopted AuNPs as the FG layer to obtain an ultra-low dark current of 10−11 A in a high-sensitivity phototransistors based on WS2, which was achieved by using the electrons captured in AuNPs to deplete the channel carrier concentration.
Based on the many possibilities of vdW stacking, different combinations of structures allow devices to exhibit different characteristics, thus achieving a wide variety of functions like information storage, photoelectric detection, and synaptic simulation. In general, there have been five typical structures of FG memory devices based on vdW materials reported so far.
Back/Top gate For FG transistors, a single-controlled gate is the most common structure. Depending on the location of the control gate, it can be divided into a back gate and a top gate structure. The back gate118-121 generally takes a heavily doped substrate under the blocking layer as the back gate electrode, and the part above the substrate is modulated by the back gate, with a simple preparation process (Fig. 2a left). However, since there is no top gate, the back gate shows weak control over the channel and requires a large voltage applied to the back gate electrode, which contributes to a large power consumption and is not conducive to the practical application of the device. Affected by the global back gate, it exhibits a large parasitic capacitance and is difficult to accomplish individual control of the device, which limits the integration of the device with other components122,123.
Fig. 2. Typical structures of FG device. a, Back (left)/Top (right) gate structure. b, Dual-gate structure. c, Semi-floating gate (SFG) structure. d, Two-terminal FG structure. e, Extended FG structure. |
Many efforts have been made to break through the currently inherent limitations of the back gate structure. Wang et al.124 relied on the large electron affinity of SnS2 as the channel material to reduce the hole injection barrier, the program voltage of the device was significantly reduced, and the device energy consumption was declined to ∼7 picojoules (pJ). To achieve individual control of the device, Marega et al.125 improved the structure by introducing a local Pd back gate, which enabled direct integration of memory and logic. Recently, many devices using indium tin oxide (ITO) as back gate electrodes have also been actively developed to expand the application of FG structure devices in various flexible electronic devices and systems126,127.
The top gate structure, in which the gate layer is deposited above the channel (Fig. 2a right), offers many advantages over conventional global back gate devices for FG memories, such as gate bias at low voltage and high-speed switching capability. The local gate bias of the top gate provides new degrees of freedom for the device, opening up novel opportunities to design devices with high integration density capabilities128. There are many FG memories utilizing top gate structures that have shown remarkable progress129-131. Park et al.132 adopted Al2O3 and HfO2 to improve tunneling efficiency with the top electrode as the control gate, they also improved the nonlinearity of synaptic weights, and successfully demonstrated linear synaptic weight update and spike time dependent plasticity (STDP) behavior as artificial synapses.
Dual-gate Due to the limitation of the weak control capability of single-gate devices, a dual-gate FG memory is proposed by improving the geometry of the memory (Fig. 2b left). The use of two control gates acting together to modulate the channel can effectively increase the control ability of gate over the channel to improve the device performance93,133,134. Rodder et al.135 proposed a dual control gate structure which employs the back gate to influence the charge storage in the FG, and adopts the top gate to change the hysteresis curve of the memory device for improving the reliability and reducing the on-state voltage. Sun et al.136 proposed a partial floating-gate field-effect transistor with the adoption of dual-gate as the top gate and control gate, which provided charge-trapping and field-regulating units, and successfully built a reconfigurable transistor and reconfigurable non-volatile memory.
Moreover, there also exists a different device structure equipped with dual-floating gate137, which realizes the separate regulation of the channel polarity through split floating gate (Fig. 2b right), making a light-triggered and polarity-switchable homojunction. This establishes a new concept for enabling light-triggered XOR logic in one single device.
Semi-floating gate The FG structure memory exhibits excellent data retention capability (about 10 years), but the inevitable charge tunneling process during operation leads to a long operation time (about 100 µs)5,138 Therefore, Wang et al.139 proposed an attractive new semi-floating gate (SFG) memory technology to fill the time scale gap between volatile and non-volatile memory technologies. After that, a SFG memory based on vdWs heterostructures appeared, as shown in Fig. 2c left, it utilizes a vdW stacking process to integrate positive and negative (PN) junctions into a FG structure for connecting channels and FG materials. Due to the ultra-high switching speed of PN junctions, the SFG memory significantly increases the write speed to the nanosecond range140. Consequently, the SFG memory can combine ultra-high operation speed with long retention time. The SFG structure compensates for the disadvantage of the slow write speed of the conventional FG memory devices, but the leakage of the PN junction inevitably affects the data retention time of the device. Ding et al.141 used the polarization of the ferroelectric gate dielectric HfZrO4 to introduce a local nonvolatile electric field to regulate the PN junction charge leakage rate, which successfully balanced the conflict between write speed and data storage.
Many innovative applications of programmable non-volatile PN junctions can also be realized with the adoption of another SFG structures (Fig. 2c right)142,143. For example, by controlling the charge storage in the SFG through the gate voltage, different rectification modes of the PN junction can be realized with rectification ratios as high as 104 to 105144,145. Sheng et al.146 used the complementary SFG FET configuration to realize the reconfigurable rectifier circuit and successfully performed memory function. Similar complementary gate-programmable PN junctions put forward promising solutions to reduce the complexity of circuit design.
Two-terminal floating gate The floating gate memory also exhibits a two-terminal structure. Compared with the three-terminal FG structure, it is the gate-free and blocking insulator-free structure, as shown in Fig. 2d. The charging and discharging behavior of the FG layer depends on the drain voltage regulation. The large potential difference between the drain and the FG layer can contribute to the charge tunneling, which will therefore achieve the purpose of storing the charge in the FG layer.
Quoc et al.94 innovatively proposed a two-terminal FG memory with the structure of MoS2/h-BN/Gr heterostructure, which shows an ultra-low off-state current of 10−14 A, and stable performance under 19% strain due to the absence of a oxide layer. With the adoption of such a similar structure, the highly reliable memristor array has been successfully demonstrated106. Li et al.147 proposed a two-terminal FG optoelectronic memory by using graphdiyne (GDY) as a photoresponsive top-FG. The device has successfully achieved more than 256 different storage levels, and the bending stability of more than 1,000 bending circles also provides a solution for flexible optoelectronic equipment. Tang et al.70 used the two-terminal FG memory to achieve high linearity and symmetric synaptic weight through simple programming of identical pulses, which successfully eliminated the additional latency and power consumption in the peripheral circuit design process. The above implies that the two-terminal FG memory could be a option for building high-accuracy and energy-efficient neuromorphic systems.
Extended floating gate In FG structures, it is usually necessary to use a large operating voltage. To overcome this drawback, extended FG geometries are proposed. Generally, the extended FG part is achieved by connecting a FG layer to a floating metal electrode. As shown in Fig. 2e, by adding the expanded FG, the total area of capacitance between the FG layer and the underlying control gate can be increased, and the increase of the effective capacitance leads to the increase of the effective gate voltage on the conducting channel, thus enhancing the coupling between the control gate and the channel. As a result, such devices can reduce the input power of the electronics by providing a very high leak-free effective gate voltage. It has been demonstrated that by increasing the area of the FG, the capacitive amplification factor can be enhanced, the subthreshold swing of the device is further enhanced, and a high degree of persistent memory for a variety of ultrathin vdW material channels can be achieved with the adoption of the expanded FG structure148,149.
Wang et al.93 have achieved the operating voltages of as low as 5 V, endurance up to 105, and a long retention time of over 105 s in the device by employing the extended FG structure whose control gate and FG layer are designed on either side of the channel layer. Based on the same structure, low power (∼7.3 fJ) programming performance of the device were achieved with the adoption of a similar high speed (50 ns), showing the advantages of such device structure in simulating heterosynaptic plasticity150. The expanded FG structure provides an exemplary role for the atomically thin quantum materials-based memristive applications with the requirement of high endurance and low power consumption.
MEMRISTORS BASED ON FG
As discussed above, FG memory exhibits a FG layer sandwiched between a blocking dielectric layer (between the FG and the substrate) and a tunneling dielectric layer (between the FG and the channel), the storage effect is achieved by trapping and releasing charge carriers in the FG layer, and the movement of charge carriers can be modulated by various stimuli. Several common memory mechanisms have been summarized and classified into electrical stimulation, optical stimulation, and mechanical stimulation, which will be described in detail below.
Electrical modulation-based FG memristors So far, in-depth investigation on the metal-oxide-semiconductor (MOS) architecture of the memristors driven by FG have already been conducted. Under the electrical stimulation, it is easy to complete the temporary storage of charges controlled by the top gate or the back gate, so that the information storage can be realized by using the charging tunnel between the channel and the FG. However, in practical applications, the three-terminal structure can lead to many issues, since relatively large pulse voltages (∼30 V) are often required, which results in relatively high energy dissipation during device operation.
Thus, Paul et al.69 achieved higher gating efficiency by attaching a graphene layer to a large-area floating gold pad with an extended graphene FG in the device (Fig. 3a). The extension of the FG increases the total area of the SiO2 capacitor (Fig. 3b), which resulted in an almost ideal subthreshold swing (77 mV/decade) and successfully reduced the drain bias voltage and switching pulses, making the memory performance more stable (Fig. 3c). The device simultaneously implements control of the Vth with a hysteresis window related to the sweep range (Fig. 3d). In this device structure, the h-BN in the middle acts as a dielectric layer separating the MoS2 channel and the FG layer, and the channel conductance is controlled by the gate, therefore the device can be used to simulate synaptic activity. The device was successfully tested for repeated potentiation and depression of the channel conductance, and the device with extended FG showed larger changes in channel conductivity than the conventional structure (Fig. 3e). This work improves the device performance by the extending FG approach, successfully increasing the possibility of integration with neuromorphic systems, and providing a new structure for synaptic devices.
Fig. 3. Extended floating gate device and electrical characteristic. a, Optical micrograph (left) and schematic diagram of the device (right). b, Representative image of the gate capacitance circuit. C1 represents the capacitance between FG and Si++ (SiO2 dielectric), and C2 represents the capacitance between FG and channel (h-BN). The extended FG is made by connecting the graphene layer to the metal plate. c, Subthreshold slopes for devices with different FG configurations. D1, D2, and D3 are devices with extended FG, D9 has no extended FG, D10 is without FG. d, Transfer curve with various Vsd. e, Changes in channel conductance of multiple potentiation and depression pulses for device structures with and without extended FG, respectively. The potentiation pulse numbers are 1 to 12 and 25 to 36, and the depression pulse numbers are 13 to 24 and 37 to 48. Reprinted with permission from ref.69. © 2014 IOP Publishing Ltd. |
The memory performance of silicon-based memristive devices decreased dramatically, which is mainly ascribed to the inevitable interfacial dangling bonds in ultrathin-body silicon. Wu et al.151 succeeded in realizing a nonvolatile and ultrahigh-speed FG memory by employing a vdW heterostructure with improved interfacial coupling and atomically sharp interfaces (Fig. 4a). Considerable hysteresis can be observed in Fig. 4c due to the higher work function of multilayer graphene (MLG) relative to monolayer graphene. On the other hand, MLG significantly reduces the interference from FG, as well as effectively suppresses ballistic currents across the FG due to low conductivity along the c-axis. The extremely uniform and clean atomically sharp interface between different functional layers in the device is an important factor for the optimized device performance (Fig. 4b). Such features enable the achievement of ultra-high-speed program/erase operations in nanoseconds for the device, and the current extinction ratio could reach as high as 1010 (Fig. 4d). Based on the above advantages, the two-bit storage with 21 ns ultrashort pulse in InSe based storage cell is demonstrated, which demonstrates that the device has the potential for multi-bit storage (Fig. 4e). This work represents a quantum leap in demand for data storage and data processing, providing the basis of optimal device engineering for next-generation electronic devices based on emerging vdW materials.
Fig. 4. Ultrahigh-speed non-volatile memory device with the atomically sharp interface and electrical characteristics. a, Schematic diagram of the device structure and working principle of the FG memory device (left). False-color optical image shows a memory device with heterostructure of InSe/h-BN/MLG placed on a SiO2/Si substrate (right). b, Large-scale HAADF-STEM image of the device. c, Typical dual-sweeping transfer curve of the device. Vds is 0.05 V. The red and blue curves correspond to the maximum Vcg of 25 V and 40 V respectively, and the arrow direction identifies the scanning direction. d, The memory cell was successfully programmed/erased by positive/negative voltage pulses of nanosecond pulse width with amplitudes of +20.2/−20.8 V, and the extinction ratio of 1010. e, An example of two-bit storage through the combination of ultra-fast pulse sequences. Among them, the voltage amplitude, and FWHM of programming and erasing pulses are (+20.2 V, 21 ns) and (−20.8 V, 21 ns) respectively. The thickness of the h-BN layer is 12 nm. Reprinted with permission from ref.151. © 2021 Nature Publishing Group. |
The large time scale gap between volatile and non-volatile memory limits the choice of memory, so a SFG structure has recently been proposed. Compared with the traditional FG structure, the introduced PN junction greatly improves the write speed of the device and retains the advantage of the long retention time of traditional FG memory devices. Liu et al.152 proposed a quasi-nonvolatile SFG memory based on vdW materials (Fig. 5a), as shown in Fig. 5b. The device could perform ultra-high speed write-1 operations in the nanosecond scale, which can be attributed to the fast charge transmission achieved by the PN junction switch formed by the WSe2 and MoS2. After 100 write-erase cycles, the output signal showed no obvious performance degradation, which also reflects the superior stability of the device (Fig. 5c and d). In particular, under the write-1 operation time of less than 20 ns, different states could still be distinguished with the wait time of 10000 ms, which means that the charge storage mode of SFG structure similar to flash memory still determines the long refresh time (Fig. 5e). In a word, as shown in Fig. 5f, the gap between volatile and nonvolatile memory technologies has been filled by the vdW materials through result of 156 times longer refresh time than DRAM and 106 times faster nanosecond write-1 operation than other memory devices, which provides a promising idea for realizing high-speed and low-power RAM device.
Fig. 5. A SFG memory and electrical characteristic. a, Schematic diagram of SFG memory. Where, WSe2, h-BN, and HfS2 are used as a channel, blocking layer, and FG, respectively. A PN junction is formed between MoS2 and WSe2. b, SFG memory write-1 at ultrahigh speed with 15 ns writing pulse. Operation process: write-read. The reading voltage VDS = 0.5 V. Performance before (c) and after (d) 100 write-erase cycles. e, The relationship between the output current and the write pulse width at different waiting times after the write operation. f, Representation of the quasi-non-volatile characteristics. Reprinted with permission from ref.152. © 2018 Nature Publishing Group. |
Optical modulation-based FG memristors With the explosive growth of data generation, conventional electrically programmed memory devices are inadequate for data storage requirements. One potential solution to this problem is to use light as a driving force to completely or partially replace electrical operation. High-performance FG-structured optical memory devices are developed with the adoption of the optical pulse control to modulate the electrical conductance state of the memory device. This enables the multi-level storage capability by adjusting the light intensity, irradiation time, or the number of optical pulses153-156. In contrast to electrical stimulation, light can provide high bandwidth, ultra-low latency and low crosstalk, resulting in increased computational speed157-159. Notably, contactless writing of optical memories requires less energy, which implies lower power consumption and higher storage levels160. Depending on the role of light in the memory device, there are types of optoelectronic memristors such as optically write memory and optically erase memory.
1. Optically-writing memristors based on FG structure Lee et al.161 developed an optically programmed multi-bit non-volatile memory device with MoS2 as the channel material and light-absorbing layer, and AuNPs are used as the FG layer to store the light-excited charge (Fig. 6a). As an optoelectronic memory, this device can exhibit a dual function. It can be programmed using negative gate voltage and erased by positive gate voltage as a conventional electronic memory. Instead of using gate voltage for programming, it also can rely on optical input and store light information as an electronic readout, thus achieving the purpose of optical programming and electrical erasing. In the optical programming process, electrons in MoS2 are excited to the conduction band in response to light stimulation, and with the assistance of a low gate voltage, electrons in the FG are transferred to the valence band of the channel layer. The transferred electrons inhibit recombination between photoexcited electrons and holes, thus allowing the long-term storage of optical signals. In Fig. 6b, the device shows excellent voltage-controlled (red area) and light-controlled (blue area) multi-level data storage characteristics, with incrementally optical power pulses on the device to achieve eight levels of data storage, and light-controlled program/erase current up to 107. The excellent retention of the device is shown in the drain current for each state remaining over 104 s (Fig. 6c), and the stability of the drain current over 200 program/erase cycles can also show excellent endurance properties (Fig. 6d). The optical signal memory device proposed above has provided an idea for all-optical logic processing and demonstrates a promising way for multi-bit photonic memory devices.
Fig. 6. Optical and electrical modulation-based FG memristors. a, Schematic diagram of the structure and working mechanism of the optical memory device with the structure of MoS2/cPVP/AuNPs. b, Optically-controlled multi-level data storage characteristics of optoelectronic memory devices applied by bias voltage. c, Retention time and d, cycle tests for MoS2 optoelectronic memory devices under photoillumination at various illumination powers. e, Schematic structure of an optical memory device based on MoS2/h-BN/graphene heterostructure with FG FETs. f, Curves of IDS with time for different pulsed light powers. Where, the exposure time texp = 1 s, VDS-read = 0.5 V, and time-dependent IDS was recorded for 20 s for each pulse power. g, The retention performance of the on-current (red, erased by a 458 nm laser pulse with a power of 200 nW for 1 s) and off-current (black, programmed by VDS-pro = -12 V for 2 s). Where, VDS-read = 0.1 V, and the thickness of h-BN is 9 nm. h, The time curve of IDS under light pulse stimuli shows the multilevel storage. Where, P = 160 nW, texp = 0.1 s, λ = 458 nm. Reprinted with permission from refs.161,162. © 2016, 2018 Wiley-Blackwell. |
2. Optically-erasing memristors based on FG structure Memristive devices with electrical programming and optical erasing have been widely adopted as well in the past few days. Tran et al.162 proposed a nonvolatile optical memory device, and notably, the device used a two-terminal FG structure with a MoS2/h-BN/graphene heterojunction. In this case, MoS2, graphene, and h-BN are used as channel, FG, and tunneling dielectric layers, respectively (Fig. 6e). When applying the negative gate voltage VDS, the electrons in the drain will be tunneled into the FG layer for storage, thus making the device display a low off-current. When applying a light pulse, the photogenerated electrons in MoS2 are blocked by the electron barrier, while the photogenerated holes in MoS2, driven by the electrons in graphene, can readily tunnel through the small triangular hole barrier into the FG for erasure. In Fig. 6f, an optical pulse power of 2 nW (corresponding to 2 nJ of optical energy) can make the device work, which shows the high optical sensitivity of the device. The large electronic barrier (≈ 2.7 eV) of the optical memory between MoS2 and h-BN ensures a high retention time extending to ≈ 3.6 × 104 s, and ultra-low off-current of ≈ 10−14 A, as well as a high program/erase current ratio of ≈ 106 (Fig. 6g). Moreover, such a design allows the device to achieve multi-level optical data storage, as shown in Fig. 6h, which separates 18 current levels as the optical pulse increases, demonstrating the reliability and effectiveness of the device as an optical memory. This new two-terminal FG memory proposed in this study focuses on overcoming the high programming voltage, high turn-off power consumption, and circuit complexity in the integration of the three-terminal optical memory, and provides a new idea to promote the miniaturization and high density of new multifunctional optoelectronic devices.
Mechanical modulation-based FG memristors Low-power and multifunctional non-volatile memristors are promising candidates for processing massive amounts of data. However, the storage state in conventional memory devices is limited by the control of electrical or optical signals. Various stimuli are urgently needed to modulate synaptic plasticity to increase the flexibility and complexity of the neuromorphic system. With the successful development of triboelectric nanogenerator (TENG), this structure with converting mechanical energy into electrical energy has been applied to various self-powered optoelectronic devices163-168. It relies on the coupling effects of triboelectrification and electrostatic induction, where a triboelectric potential is triggered by a mechanical motion stimulus to replace the conventional gate voltage action. This chapter utilizes the synergistic function of TENG and FG for charge capture to achieve mechanically controlled nonvolatile storage functions, and such memories also provide a new way to achieve simulations of more complex synaptic behavior.
Jia et al.169 proposed a non-volatile, mechanical modulated FG structure memory device composed of a graphene/h-BN/MoS2 heterojunction and a TENG in contact-separation mode. The TENG structure is attached to the back gate of the heterojunction transistor. When the friction layer polytetrafluoroethylene (PTFE) controlling the TENG approaches or moves away from the removable Cu electrode layer, this behavior will induce positive or negative potentials, thus modulating the charge transfer to the FG layer and completing the program/erase processes (Fig. 7a). In terms of cycling, the stable switching behavior of the mechanically regulated memory at short displacement shows that it is no less stable than the electrical regulated memory (Fig. 7b). The program/erase current ratio up to 105, achieved by mechanical displacement, also provides the basis for its multi-bit storage capability (Fig. 7c). Achieving multi-bit storage can be complished in different ways, and successive application of displacement is one of the potential ways. As shown in Fig. 7d, a successive step displacement of 0.05 mm is applied after programming, and the resulting potential will cause the FG layer to capture more charge, leading to a separated 7 current states. Separating the current states using different displacements is another approach. As shown in Fig. 7e, different displacements are applied on the off-current, and the memory is successfully programmed to 14 separated current levels, validating another possibility of multi-bit storage for the device. This work demonstrates the superior performance of FG structure memory devices combined with TENG, which is not inferior to purely electronic-controlled devices. Such devices could shed a light on the development of multi-level data storage, multi-functional human-computer interaction and low-power consumption, etc.
Fig. 7. Mechanical modulation-based FG memristors. a, Schematic structure of a tribotronic nonvolatile memory based on graphene/h-BN/MoS2 heterojunction combined with TENG structure. b, Endurance test with 100 cycles regulated by TENG displacement. Among the contents of the cycles: programming at a relative distance of −0.2 mm for 3 s (blue area), erasing at a relative distance of +0.2 mm for 3 s (orange area), and the reading voltage VDS = 50 mV for 1 s. c, Retention performance of the memory after applying the reverse mechanical displacement, where VDS = 50 mV. d, The time of IDS with the increasing distance between two friction layers. The separated states show the potential of multi-level data storage in memory, where the fixed step distance is 0.05 mm. e, The time curve of IDS at different interval distances from 0.01 mm to 0.25 mm. Reprinted with permission from ref.169. © 2021 Elsevier B.V. |
The correlation analysis of bio-mechanical and visual information is fundamental to the perceptual capabilities of the human brain, and connecting mechanical and optical signal is essential for recognizing the external environment and promoting interactive artificial intelligence. To promote multimodal interaction and coupling diversity in devices, Zhao et al.170 reported a novel memory device by combining optical and mechanical modulation with FG structure. In particular, the device employed high-density quasi-continuous nanographene as FG, which effectively increases the storage capacity due to its adept charge-storing property. This design can perform the programming/erasing task with the adoption of both mechanical and optical input modes (Fig. 8a). As shown in Fig. 8b, when applying the corresponding mechanical pulse, a positive voltage is generated to drive electrons tunneling from the channel into the FG layer, and electrons can be trapped. On the contrary, when a mechanical pulse with the opposite displacement or an appropriate optical pulse is applied, the resulting negative voltage drives electrons in the FG layer to tunnel back into the channel, thus presenting a different channel conductance. In this design, TENG plays an important role in the device's operation. The device can exhibit a stable current state for at least up to 105 s by testing the programming/erasing state with different displacements, and it shows a high programming/erasing current ratio of 107 (Fig. 8c). In addition, the device exhibits stability of 200 cycles in the optical input mode with the utilization of different incident optical power (Fig. 8d). Moreover, applying different optical powers can control the degree of photon absorption and thus indirectly affect photoresponsivity. As shown in Fig. 8e, when the optical power is 0.01 µW (corresponding to a gate voltage of 80 V), it will produce a photoresponsivity of ∼12000 A/W, which reflects the high photoresponsivity of the transistor device. The synergy of mechanical modulation and optical modulation can be reflected in Fig. 8f-h. The successive displacements of Fig. 8f can generate the corresponding gate voltage, and the current of the device can be successfully separated into 10 successive current states (green area in Fig. 8h). After the erase operation, the applied stepped optical pulses of Fig. 8g also make the device show different storage states (yellow area in Fig. 8h). Mechanical/optical modulation ensures the multi-bit storage capability of the device. Self-powered triboelectric potential gating and high-bandwidth optical programming hold the promise of leading mechanical-optical devices beyond the von Neumann architecture, with low power consumption and versatility, and dual-mode regulation providing a new perspective on future artificial intelligence interaction behavior.
Fig. 8. Mechanical modulated FG memristor based on dual mode input. a, Mechanical modulated non-volatile memory. Coexisting of optical and mechanical input realize the multilevel storage function together. b, Energy band diagram of the working principle of device programming and erasing processes. c, Retention time of the memory device after different TENG displacement operations, where VD = 1 V. d, Program/erase cycle test of the memory device after various laser pulse illumination. e, Device photoresponsivity versus mechanical displacement (corresponding to different gate voltages) at different optical powers, where VD = 1 V. h, The different states of the drain current when the voltage pulse (f) generated by the mechanical displacement and the optical pulse (g)is applied to the memory device, respectively. Reprinted with permission from ref.170. © 2020 Elsevier B.V. |
APPLICATIONS FOR NEUOMORPHIC COMPUTING
Neuromorphic computing, which utilizes artificial neurons and synapses, presents a viable solution to build a distributed, fault-tolerant, low-power intelligent system171,172. Among the various options of the device structure, the FG structure with a unique charge-trapping layer makes it an ideal candidate for simulating synaptic plasticity in a single device, which is crucial for the development of multifunctional neuromorphic systems based on electronic devices173, particularly in the field of visual recognition, such as handwritten digit recognition, etc73,174-176.
Visual recognition The neuromorphic vision systems (NVSs) based on vdW material photoelectric synaptic devices show great potential in neuromorphic visual computing and image processing. In the process of single target recognition, synaptic plasticity can be modified to distinguish target signals and noise signals by accumulating external visual signals, which can improve the accuracy of NVS recognition. Nevertheless, when multiple objects exist in the scene, objects with weak visual signals are frequently eliminated as noise, which makes it difficult to identify multiple targets. By adopting light and electrical stimulus-sensitive FG synaptic devices to integrate external stimulation with internal attention signals, Chen et al.177 successfully established an NVS with biological attention mechanism (Fig. 9a) and multi-target recognition was achieved. As shown in Fig. 9b, an integration-type synapse that mimics attentional mechanisms can modulate synaptic plasticity by integrating optical stimuli and attentional signals to produce postsynaptic signals. By using gate voltage Vgs pulses as the electrical stimulation for attention modulation and laser pulses as the external visual stimulation, the FG device with ReS2 photosensitive channel can implement integrated synapses perfectly. As shown in Fig. 9c, light spike stimulation could increase the concentration of photogenerated carriers in ReS2, and positive gate voltage could pulse drive channel carriers into the FG, and both of them could contribute to the modulation of the channel conductance. The resulting long-term potentiation and long-term depression behaviors successfully modulate synaptic plasticity, which is the basis for achieving multi-target recognition tasks. Before performing the multi-target recognition task, the attentional stability of the NVS built from an array of integration-type synapses was first demonstrated (Fig. 9d). In the recognition of the number "2", voltage pulses were used to introduce attentional fluctuations in the system, and the recognition of feature map by NVS resulted in an average recognition probability (98.19%) with a standard deviation (0.28%), which still approximates the recognition probability (98.23%) of the target under attention stabilization. The NVS with attention mechanism consists of a photoelectric synapse array for perceptual processing of visual information and the (artificial neural network) ANN for processing feature map, as shown in Fig. 9e. Notably, based on the attention mechanism model, the gate voltage can reconfigure visual information stored synaptic array, therefore selective target recognition can be achieved by simulating the focus attention mechanism (Fig. 9f). Finally, the simulation results of NVS with attention mechanism are shown in Fig. 9g. Due to the difference in external stimulus intensity, the NVS based on the saliency attention mechanism could only recognize the target "8" ((i)-(ii)), while the numbers "2" and "6" are just captured by the synaptic array and monitored via the threshold value segmentation method. Subsequently, synaptic plasticity is regulated according to the attentional mechanism model, which means that the focal attention is shifted by applying the gate voltage, thus the "2" and "6" are recognized sequentially ((ii)-(iii) and (iii)-(iv)). Finally, the multi-target recognition task is successfully executed. This work introduced biological visual attention mechanisms into NVS by integrating optoelectronic signals, which could process overloaded visual information effectively and provide new inspiration for how to allocate limited computing resources to achieve visual cognition.
Fig. 9. All vdW integration-type optoelectronic synapses for multi-target recognition. a, Schematic illustrations of biological visual attention mechanism in multi-object recognition tasks. Saliency-based attention (blue path): The visual cortex forms feature maps through perceptual memory processes, and the human visual system identifies the most salient target. For instance, the dark “8” is more likely to be recognized in the figure than “2” and “6”. Focus attention mechanism (orange path): the prefrontal cortex is involved in attentional control, regulating the representational salience of external stimuli by focusing attentional signals to identify non-salient objects. According to the priority determined by the focus attention mechanism, the non-salient “6” or “2” can be recognized. b, Left: schematic diagram of an integration-type biological synapse. Visual and attentional signals can be integrated to identify postsynaptic signals. Right: schematic diagram of artificial synapse with integrated functionality based on ReS2/h-BN/monolayer graphene structure. c, LTP/LTD behavior of the integration-type synapse. 20 continuous light spikes (0.11 nW µm−2, 100 ms, interval 100 ms) were applied to trigger the LTP behavior, and 20 consecutive positive gate voltage pulses (from 0.05 to 9.55 V with 0.5 V step at Δt = 200 ms) were applied afterward to trigger the LTD behavior. d, Recognition probability distribution of 100 random feature maps under attention fluctuation conditions. Each unit in the “2” area of the synaptic array was set to the same normalized conductance value of 0.8 during the steady attention state. Three Sine function gate voltage pulses (amplitude 0.1 V, period 2 s) and five Sine function gate voltage pulses (amplitude 0.2 V, period 2 s) are applied to simulate the periodic fluctuation of attention. The resulting volatility normalized conductivity (from 0.75 to 0.85) is then randomly assigned to the “2” area, allowing 100 feature diagrams to be formed, and the recognition probability is obtained by inputting the feature maps into NVS. e, Illustration of a NVS for the multi-target recognition task, with a visual attention mechanism based on an optoelectronic synapse array. The synaptic array captures three targets (distinguished by different light doses) and converts light doses into corresponding conductance. In the output feature map, by mapping conductance to grayscale, the most salient target is input into ANN for recognition. In particular, the selective recognition of the target is controlled by the voltage. f, Schematic diagram of the process that identifies three targets with varied saliencies in turn, relying on saliency-based and focus attention mechanisms. g, Recognition possibilities for three targets (“8”, “2”, and “6”) about attention modulation number. Reprinted with permission from ref.177. © 2022 Wiley-VCH Verlag. |
Auditory recognition Auditory and visual perception serves as crucial mechanisms for organisms to gather information from the external environment. Paul et al.178, reported that the FG MoS2 device (MoS2 FG-FET) (Fig. 10c) could be used to build a neuromorphic speech recognition system(NSRS) based on STDP learning rules, which replicates the human auditory pathway and performs a range of auditory recognition tasks. The NSRS is made up of a cochlea model, an unsupervised feature learning stage, and a simple linear classifier (Fig. 10a). Firstly, the sound waves were supplied as neural spikes based on the cochlear model, then a MoS2 FG-FET with electric field-related FN tunneling behavior was used, and synaptic plasticity of the STDP learning rule was simulated in the neural network. Finally, a linear classifier was employed to check the systematic classification performance of the target application. This system operates based on the Hebbian learning rule with an emphasis on the timing of spikes between pre- and post-synaptic neurons. The change in the conductivity of the device depends on the overlapping of pre-and postsynaptic spikes, and a typical spike modeling approach is shown in Fig. 10b). By adopting isolated digits from the TIDIGITS database, the proposed neuromorphic auditory system was tested against the database and the accuracy of 88.92% on 3260 spoken digits was realized (Fig. 10d). The system demonstrates a novel neuromorphic architecture for auditory tasks, specifically in the area of spoken digit recognition. The main advantage of the system is that it makes use of the intrinsic plasticity of the MoS2 device to model the STDP rule as a synaptic memory in a single device, which eliminates the need for any other learning circuitry. Compared with conventional classification networks, the complexity and memory requirement of the system was significantly decreased by the proposed approach.
Fig. 10. MoS2 FG-FET for neuromorphic speech recognition. a, A block diagram comparing the proposed NSRS with its biological counterpart. The functions of the basilar membrane (BM) and inner hair cells (IHC) are simulated by the cochlear processing unit, which is in control of filtering frequency information from the audio sample and transmitting it non-linearly, and finally outputting spectrogram of digits 0 to 9. Spiral ganglion cells (SGC) were modeled as Poisson neurons, and features were extracted through STDP layers to output neurons, whose postsynaptic potentials were used to perform speech recognition tasks on TIDIGITS isolated digits. b, Typical shape of bio-realistic spikes used in the STDP layers. c, Schematic diagram of the MoS2 FG-FET used for STDP learning. d, Confusion matrix for a speech recognition task of 3260 spoken digits performed on the TIDIGITS dataset. The x-axis represents the audio's actual class/digit, while the y-axis represents the class/digit predicted by the classifier for the provided audio. Therefore, the higher the value on the diagonal in the confusion matrix, the more accurate the prediction. Reprinted with permission from ref.178. © 2014, IOP Publishing Ltd. |
Tactile recognition Due to the significance of tactile information in intelligent human-computer interaction, the study of tactile recognition systems has been a key focus of research in neuromorphic computing. To enable complicated biological tactile functions, Mo et al.179 constructed a tactile recognition system by combining a MoS2 synaptic transistor (Fig. 11a) with a micro-structured polydimethylsiloxane (PDMS) pressure sensor (Fig. 11b). The system structure is shown in Fig. 11c. The sensors are placed at different locations, as shown in Fig. 11d, when the sensors are touched in turn, the output current levels will differ due to the different channel lengths of the transistors connected to the sensors, and the tactile system can use this principle to detect the spatial location of the touch. The reliability of spatial position recognition is reflected in the stable response current of the same sensor (Fig. 11e). Spatiotemporal modulation of synaptic plasticity can be achieved simultaneously in the system, i.e., temporal modulation of synaptic weight simulated by a series of Vgs pulses and spatial modulation of synaptic weight simulated by different pressure sensor touches. The post-synaptic current achieves five types of synaptic plasticity when modulated by different Vgs pulses and channel lengths, as shown in Fig. 11f, which indicates the potential for more flexible tunability of synaptic weight. Flexible synaptic plasticity provides the foundation for simulating the physiological learning and forgetting behavior of the human brain. While in real life, easy knowledge takes less time to learn and more time to forget than difficult knowledge, so the difficulty of different learning activities also needs to be simulated in the device (Fig. 11g). As shown in Fig. 11h, the learning efficiency and forgetting speed in this tactile system can be selected by touching different pressure sensors, which perfectly matches the various learning and forgetting behavior patterns of the human brain. The artificial synapses shown here expand the application of touch-related artificial neuromorphic networks, which provides favorable options for interactive sensory recognition.
Fig. 11. Intelligent tactile recognition system. a, Cross-section TEM image (left) and top-surface SEM image (right) of MoS2 synaptic transistor. Among them, MoS2 is the channel layer and AuNPs is the FG layer. The transistor has five channel lengths, L = 3, 9, 15, 21, 27 µm, with one source electrode (S) corresponding to five drain electrodes (D1, D2, D3, D4, D5). b, SEM image of PDMS film (top) and structure of PDMS pressure sensor (bottom). The PDMS film has unique pyramid micro-structures, which are covered with a Cr/Au (5/40 nm) layer as a top electrode (TE). The ITO on the PET film is used as a bottom electrode (BE). c,The diagram of the integration of MoS2 synaptic transistor and PDMS pressure sensor, wherein the drain electrodes D1, D2, D3, D4, and D5 are connected with the pressure sensors S1, S2, S3, S4, and S5, respectively. d, Illustration of spatial position recognition. The pressure sensors S1, S2, S3, S4, and S5 are distributed in the east, south, west, north, and center directions, respectively. e, Results of the spatial position recognition. The response current changes with time as each of the pressure sensors S1, S2, S3, S4, and S5 is pressed. f, Spatiotemporal modulation of synaptic plasticity is controlled by touching different pressure sensors. g, Diagram of spatiotemporal modulation of synaptic plasticity (top), and learning and forgetting activities (bottom). The difficulty degrees of learning activities are represented by different pressure sensors, S1, S2, S3, S4, and S5 represent very easy, easy, normal, difficult, and very difficult, respectively. h, Simulation of various learning and forgetting abilities controlled by touching. The required number of Vgs pulses for S1, S2, S3, S4, and S5 to obtain the same ∆W increment are 10, 20, 40, 50, and 70, respectively. However, it is noteworthy that the ∆W decays to 39%, 25%, 19%, 9%, and −12% for S1, S2, S3, S4, and S5 after removing the Vgs pulses for 100 s. Reprinted with permission from refs.165,179. © 2016 Elsevier B.V. © 2023 Wiley-VCH Verlag. |
CHALLENGES OF NEUROMORPHIC DEVICES
This paper provides a comprehensive review of FG memristor devices based on vdW materials. The FG structure has received a lot of attention due to its unique FG layer. In particular, the basic principles of the FG memristor device was provided, the devices were classified into electrical modulation-based memristors, optical modulation-based memristors, and mechanical modulation-based memristors depending on the stimulus type they receive during modulation. Finally, the application of the FG memristor device in neuromorphic computing was also introduced in detail.
VdW materials and their heterostructures offer diverse possibilities for synaptic devices. Devices based on vdW materials are often endowed with many advantages over bulk materials, such as the absence of dangling bonds on the surface, lattice mismatch free, and sensitivity to external stimuli. On this basis, high-performance and low-power neuromorphic computing architectures can be designed and fabricated. However, some technical challenges still remain to be resolved for better device performance.
Searching new vdW materials for FG memory devices Currently, vdW materials, such as graphene and MoS2, have been extensively investigated and utilized in FG memory. However, some existing vdW materials exhibit inherent drawbacks such as difficulty in preparation, low stability and reliability, which limits their practical applications. Based on the bandgap modulation mechanism, unique new vdW materials can be explored to replace the dielectric layer, FG layer, and channel layer in FG systems, so that they can achieve transient response under ultra-short programming and erasing pulses. The goal is to achieve a larger storage window and longer retention time while reducing the number of vdW heterojunction layers, thereby further optimizing the performance of the device. Searching for new vdW materials is expected to provide higher design freedom and functional diversity, expanding the development space of FG memories.
Developing new tunneling mechanisms The tunneling process determines the storage speed and energy consumption of FG memory. However, there still exist many limitations to the known vdW material-based tunneling mechanisms. For example, the high voltage required for FN tunneling can lead to unavoidable high energy consumption, and direct tunneling through a thinner tunneling dielectric layer may weaken data retention ability, which will reduce the reliability and performance of the memory78. Developing a novel tunneling mechanism can provide higher switching speed and erase/program ratio, lower power consumption, and higher storage density, which brings breakthroughs in performance and applications for vdW material FG memory.
Designing a more reasonable FG device structure The reasonable design of the FG device structure is a decisive factor in enhancing the performance of vdW material FG memory. For example, new functional layers can be introduced into device structures to realize multifunctional devices, and the FG structure can be optimized to improve memory performance. By constantly exploring and optimizing device structures, it is possible to achieve high-performance, multifunctional, and multi-modal modulated FG memory with multi-bit storage capability, thereby further promoting the development of FG memory.
Reducing the interference during miniaturization With the increased integration density of the FG cell, the miniaturization of the device is imminent, and the resulting capacitive interference between neighboring cells and the reduction of gate-coupling ratio cannot be ignored41,104. Due to the shorter distance between the units, the FG voltage between adjacent units is coupled by a parasitic capacitor, which will cause the threshold voltage of the device to be unexpectedly offset102,103. Similarly, with the continuous scaling down of the gate, the gate-coupling ratio decreases, which will greatly affect the switching characteristics of the device. Researchers have tried a variety of methods to overcome the above problems, such as reducing the thickness of the FG to reduce cell-to-cell interference, and using high-k dielectric materials as tunneling dielectrics to increase the gate-coupling ratio180. Other methods should also be further explored to overcome the difficulties encountered in device miniaturization.
In summary, in order to promote the application of memristors with FG structures based on vdW materials in future neuromorphic electronics, not only the above problems should be resolved firstly, but also the material preparation, device design, processing, and circuit integration should be modulated for better mimicking human self-learning and cognitive abilities based on neuromorphic computing activities.
MISCELLANEA
Acknowledgments This work was supported by Beijing Natural Science Foundation (Grant No. Z210006), the National Key Research and Development Program of China (Grant No. 2022YFA1405600) and the National Natural Science Foundation of China (Grant No. 12104051).
Declaration of Competing Interest The authors declare no competing interests.
