INTRODUCTION
Over the past decade, quantum computers have attracted significant attention due to their unparalleled computing capabilities in solving specific problems that are intractable for classical computers, such as prime factorization, quantum medical analysis, etc1-3. Quantum bits (qubits) are operated in an ultra-low temperature environment provided by a dilution refrigerator, typically in the range of a few tens of millikelvin, and manipulated with the adoption of microwave-driven controlled evolutions and flipping operations. To accurately read out and control the quantum processor, a classical control interface is typically employed, which is implemented today with commercial instruments operating at room temperature (300 K) and connected to the qubits via coaxial cables. However, as the number of qubits grows towards thousands and millions, the corresponding increasing number of long cables also bring challenges, including heat leakage and time delays, which significantly influence the temperature stability inside the dilution refrigerator and complicate the measurement process. Practical quantum computing applications require stable manipulation and readout of millions of qubits, demanding scalability in quantum computing systems. To overcome this bottleneck, a cryogenic electronic interface that operates in close proximity to the quantum processor is proposed4-6. This readout and control interface is placed in the 1 to 4 K temperature zone of the refrigerator, which reduces the temperature leakage, minimizes the path of high-frequency signals, and mitigates the complex interconnection challenges between the cryogenic qubits and room temperature instruments. Therefore, researches on low-temperature electronics and IC for quantum computing applications have become active issues and attracted more and more attention over the past few years3-20.
Although a cryogenic analog-to-digital converter (ADC) for RF readout of large-scale spin quantum bits has been presented7,15, its clock signal is currently sourced from an oscillator at room temperature, which increases the complexity and limits the scalability of system interconnection. Therefore, as shown in Fig. 1, a local cryogenic clock generator is required to generate clock signals for the components (such as ADC, DAC, etc.) in the qubit control/readout circuits. Firstly, the electrical characteristics of cryogenic CMOS (cryo-CMOS) devices deviate significantly from those at room temperature. Commercial models of CMOS devices are typically designed for an applicable temperature range of 40 to 125 °C21-23. Therefore, it is necessary to conduct characterization and modeling of cryo-CMOS devices to address the availability of the compact model. Cryogenic circuit architectures also need adjustment to accommodate the characteristics of cryo-CMOS devices for reliable operation at such low temperatures.
In the current work, SMIC 180 nm CMOS transistors were characterized at temperatures ranging from 300 to 4 K. Based on the commercial BSIM3v3 model, a cryo-CMOS model available for 4 K simulations was developed to aid in the design of cryogenic circuits. This model incorporated the correction of low-temperature effect and parameter optimization with the adoption of a machine learning (ML) approach. On this basis, this work demonstrates a cryo-CMOS clock generator optimized for 4 K operation. The clock generator exhibits an output frequency range of 450 to 850 MHz. At the output frequency of 600 MHz, it achieves −95.53 dBc/Hz with 10 kHz offset and −102.73 dBc/Hz with 1 MHz offset phase noise, < 4.8 ps RMS jitter, and −39.32 dBc reference spur with 30 mW power consumption (with test buffer), which is corresponding to a jitter-power FOM of −211.6 dB at 4 K.
This article is organized as follows. In Section II, a description of cryogenic device characterization and the developed 4 K CMOS model for circuit design is provided. Section III elaborates on the clock generator architecture and cryogenic circuit design considerations. The measurement results of the clock generator at 300 K and 4 K are presented in Section IV, and finally, the article is concluded in Section V.
CRYOGNEIC DEVICE CHARACTERIZATION AND MODELING
Cryo-CMOS Characterization
The low-temperature behavior of devices deviates from that at 300 K, leading to a necessary re-characterization and modeling process. As shown in Fig. 2, the electrical properties of the 180 nm CMOS technology were characterized in a wide temperature range of 300 to 4 K. Due to the relaxation of the Boltzmann thermodynamic limit (kBT/q), the subthreshold swing (SS) tends to be steeper with decreasing temperature (Fig. 2a and c), which means that the switching speed of the devices tends to be faster at low temperatures. Due to the weakening of lattice scattering, the mobility is optimized and then the drain current (IDS) and the transconductance (Gm) are improved, as shown in Fig. 2a and b. The low-temperature mobility is mainly determined by surface roughness scattering, thus the mobility reduction resulting from the vertical field at large VGS bias is more significant at low temperatures, which even leads to negative Gm behavior at VGS = 1.8 V in Fig. 2b. Fig. 2d shows the output characteristics in 10 µm/180 nm NMOS at different temperatures. As expected, the on-state current (ION) increases gradually as the temperature decreases, especially between 77 and 300 K. It is worth noting that, at 4 K when VDS > 1.4 V, IDS exhibits a significant unsaturated characteristic, which leads to a significant reduction in transistor output impedance. This phenomenon is caused by the “kink effect”24,25 and will be discussed in the next subsection. Therefore, it is necessary to avoid transistor bias within this range (VDS > 1.4 V) in circuits that are sensitive to output impedance, such as amplifiers or current sources. The saturation region transfer characteristics and the extracted threshold voltage (VTH) are shown in Fig. 2e and f. The gate-induced drain leakage (GIDL) effect and the off-state (IOFF) current are significantly optimized at low temperatures (fig. 2e). At low temperatures, the larger band gap elongates the band-to-band tunneling (BTBT) distance and thus reduces the GIDL current23. It means that the on-off ratio is improved and the static power consumption in the digital circuit is greatly reduced. VTH is extracted at the threshold current ITH = 1.0 × 10−9 W/L (A). Compared with room temperature, VTH increases by ∼300 mV at 4 K in both 10 µm/10 µm and 10 µm/180 nm transistors, which can be attributed to the bandgap (Eg) widening and the scaling of the Fermi-Dirac function26-28. The intrinsic carrier concentration ni is extremely small at low temperatures and thus leads to a large inversion threshold 2ϕF = 2kBT/qln(Na/ni), where, Na is the substrate doping concentration. Therefore, a higher supply voltage is required to overcome the increased VTH at low temperatures, however, it results in additional power consumption. To overcome the trade-off of power consumption and frequency, low-VTH devices, adjusting VTH by substrate bias, and back-gated silicon-on-insulator technologies are favorable choices for cryo-CMOS circuits design.
Fig. 2. Cryo-CMOS characterization and modeling. a, IDS-VGS curves and b, The transconductance of 10 µm/10 µm NMOS with VDS = 50 mV. c, Linear region transfer characteristics, d, output characteristics, and e, saturation region transfer characteristics of 10 µm/180 nm NMOS. f, VTH versus temperature in 10 µm/10 µm and 10 µm/180 nm NMOS. g, RMS error versus optimization generations an example cryo-CMOS parameter optimization process. After kink correction and ML-assisted parameter optimization, the measurement (symbol) and model calculation results (solid line) of the h, saturation region transfer characteristic and i, the output characteristic at 4 K. |
To guide the cryo-CMOS circuits design, the low-field mobility of NMOS and PMOS (μn and μp) is estimated at VDS = 50 mV by the Y-function (the ID/√Gm method)29,30. The extracted results are shown in Table 1. At room temperature, the ratio of μn to μp is about 3.7 : 1, but it tends to be 5.9 : 1 at 4 K. In digital circuits, to ensure that the rising time of the output signal is consistent with the falling time, the size of PMOS must be much larger than that of NMOS so as to achieve sufficient pull-up capability. Therefore, the digital standard cell libraries need to be redesigned. Different from μn, μp at 77 K is slightly larger than that at 4 K. In order to adjust the VTH of PMOS, a light boron implant was performed in the channel, which leads to the formation of buried channels. Due to the freeze-out of the implant, the peak mobility of the buried channel is around 80 K31,32, thus μp at 77 K is slightly larger than 4 K. In addition, the Gm-VGS curve changes more dramatically at low temperatures (Fig. 2b). This phenomenon may deteriorate the linearity of circuits, such as amplifiers, and thus aggravate the total harmonic distortion (THD). In addition, the mismatch of the current factor (β) and VTH deteriorates as well at cryogenic temperatures33, leading to an additional challenge. Based on the above analysis, it is necessary to establish a cryo-CMOS model to assist in low-temperature circuit design.
Table 1. Mobility of 10 µm/180 nm MOSFETs at 300 K, 77 K, and 4 K. |
| Temperature (K) | 300 | 77 | 4 |
|---|---|---|---|
| μn (cm2/V·s) | 145.9 | 993.3 | 1066.5 |
| μp (cm2/V·s) | 113.3 | 182.8 | 181.5 |
| μn/μp | 3.7 | 5.4 | 5.9 |
ML-assisted parameter optimization and modeling
As reported25, the standard compact model is able to cover cryogenic operation without significant modifications (e.g. BSIM21, EKV22, PSP34). The low-temperature CMOS characteristics are described by updating the parameters of the standard commercial model. The Eg widening-induced VTH shift can be described by adjusting the VTH-related parameters, the weakening of lattice scattering can be described by adjusting the mobility-related parameters, and mobility reduction due to the vertical field is already included in the original BSIM model. Besides, although most of the commercial models are based on the Boltzmann statistics, the Poisson-Boltzmann equation is still effective even under deep-cryogenic temperatures27. In order to obtain more accurate cryogenic model parameters, a machine learning-assisted parameter optimization program was developed. A modified evolutionary strategy (MES) was proposed to optimize the default parameters of the BSIM3v3 model21nd the (1 + 1) evolutionary strategy35as employed in the MES. The mutation is the foremost step in MES and the equations of the mutation operation are presented as follows:
Where, Genei(child) is the value of (i + 1)th parameter of the child generation and Genei(parent) denotes the value of (i + 1)th parameter of the parent generation. The vector of child parameters is written into the model equations after the mutation operation so as to calculate the simulation value. The RMS error and the fitness are defined as:
Where, N denotes the number of data points, Imeasi, Icalci, and Imeasimax represent the measurement data, calculation results, and the maximum measurement value, respectively. The fitness is the average RMS error of different electrical characteristics in CMOS transistors. According to the fitness value, the program selects the better parameters’ vector from the child and parent as the parent of the next generation until the optimization process is completed. An example optimization process is shown in Fig. 3a: the RMS error decreases monotonically until convergence during the parameter optimization process. To ensure the rationality of the parameters, the model parameters are corrected, adjusted, and ML-assisted optimization multiple times during the modeling process.
Fig. 3. Design details of cryo-CMOS clock generator circuit. a, The circuit structure of the cryogenic clock generator. b, The circuit structure of the double-edge receiving ring oscillator. c, The schematic diagram of the internal module circuit. d, Oscillation frequency comparison between the double-edge receiving ring oscillator and the conventional differential ring oscillator. e, The circuit structure of the charge pump. f, Charging/discharging current versus output voltage. g, The circuit structure of the multi-mode frequency divider. h, The circuit structure of the phase-frequency detector. |
Besides, the non-ideal effects need to be additionally corrected. The kink effect can be effectively avoided in processes below 160 nm node36, but it remains an additional challenge for 180 nm cryo-CMOS modeling (Fig. 2d). The physical explanation of the kink effect dates back to three decades ago24,37-39. At low temperatures, the substrate is so resistive that it is at floating potential due to the carrier freeze-out. The holes produced by impact ionization flow to the freeze-out substrate and accumulate, raising the floating substrate potential. Hence, VTH is reduced and IDS increased, which thuscontributes to the kink effect38,39. Following the above physical mechanism, the revised threshold voltage (VTH_kink) can be expressed as:
Where, ΦF denotes the Fermi potential, γ is the substrate bias effect coefficient. Vbulk is the potential of the freeze-out substrate and can be calculated by Vbulk = Isub × Rbulk, where, Isub represents the substrate current and Rbulk is the substrate resistance related to Isub25. The modified VTH_kink is written into the original model and then the corrected IDS is calculated. As shown in Fig. 3b and c, the simulation results of the model and the measurement results are well-fitted in the subthreshold, the saturation, and the kink region. However, the accuracy of the proposed model is limited. This parameter-fitted model is not a low-temperature physics-based compact model and many of the low-temperature effects (e.g. incomplete ionization26,40,41, quantum transport42, source-to-drain tunneling43,44, etc.) have not been taken into consideration. Besides, the Monte-Carlo parameters, parasitic capacitors, self-heating effect45, mismatch parameters33, and small-signal model46f cryo-MOSFETs also need further investigations and modeling. These works will be carried out in our next stage of cryo-CMOS modeling researches.
CRYO-CMOS CLOCK GENERATOR
Based on the above research, a 180 nm process cryogenic clock generator for the control and readout electronics of qubits was presented. In order to meet the stringent requirements of a comprehensive index, a charge pump phase-locked loop architecture was adopted for the clock generator in the design, as shown in Fig. 3a. Additionally, the off-chip loop filter was adopted since the performance of the on-chip passive devices at low temperatures cannot be accurately predicted. The division ratio of the divider can be adjusted between 16 and 31 with the adoption of a 4-bit digital signal. Due to freeze-out in the base at 4 K, the severe degradation of the bipolar junction transistor (BJT) characteristics precludes the design of a bandgap reference or low dropout regulator (LDO) to provide circuit bias provision. However, as the operating temperature for this design was fixed at 4 K, the absence of the bandgap reference will not have a significant impact. Besides, the clock generator prioritizes parameters such as frequency tuning range and chip area over-achieving high phase noise performance. Consequently, a ring oscillator-type voltage-controlled oscillator (VCO) was adopted instead of the inductor-capacitor (LC) oscillator type in the current design.
Double-edge receiving ring oscillator
The use of ring oscillators in clock generator design is widespread due to the absence of inductors and capacitors. Current-starved ring oscillators are particularly popular owing to the advantageous characteristics of simple structure, lower transistor count per unit, and low intrinsic noise. However, their single-ended circuit design makes them vulnerable to substrate or power supply noise. To mitigate this issue, differential ring oscillators have become the more popular choice for VCO designs as they could provide superior phase noise performance. It consists of a set of differential pairs, a pair of PMOS load transistors, and a positive feedback load section. Frequency control is accomplished by adjusting the strength of positive feedback, which affects the delay of each stage. The traditional differential ring oscillators only adopt NMOS transistors to receive the previous stage's signal. However, at cryogenic temperatures, the VTH increases by ∼300 mV, which has a negative effect on the turn-on time of the transistors. To address this issue, the cryogenic clock generator utilizes a double-edge receiving ring oscillator structure, as shown in Fig. 3b.
Unlike the conventional structure, the PMOS transistors in the delay unit, i.e. M7 and M8 (Fig. 3c), can receive signals from the stage before the previous module through an additional transmission path (the green path). As a result, the waiting time for PMOS transistors to turn on is significantly reduced during an oscillation cycle, which enables faster signal reversal and increased output frequency without significant power consumption47,48. Additionally, according to phase noise analysis theory49,50, the reduction in rise time results in better VCO phase noise performance by reducing the injection noise of the PMOS transistors. With the utilization of the additional transmission path, the double-edge receiving ring oscillator is able to achieve a frequency range of 370 to 870 MHz, which is nearly double the frequency range of the conventional single-edge receiving oscillator that only ranges from about 133 to 468 MHz, as shown in Fig. 3d.
Charge pump
Fig. 3e shows the detailed structure of the charge pump, which adopts the drain switch structure with current steering switches51. To suppress the in-band noise of the PLL, the charge pump current is set to 50 µA. The good DC current matching performance of the charge pump at 4 K is shown in Fig. 3f, with only 2.1% maximum DC mismatch when the output voltage is ranged between 0.2 and 1.6 V.
Multi-mode frequency divider
As shown in Fig. 3g, the multi-mode frequency divider is comprised of four 2/3 dual-mode frequency dividers, which enables integer frequency division between 16 and 31. The frequency of the divider is mainly determined by the D flip-flop (DFF). As the maximum output frequency of the VCO approaches 900 MHz, with the possibility of even higher measured frequencies, the first two stages of the dual-modulus prescaler were designed with the true single-phase clock (TSPC) DFF. Incorporating the TSPC-DFF in the design decreases the number of MOS transistor stacks from power to ground, resulting in reduced signal transmission delay and a substantial improvement in operating frequency52. Additionally, a faster high-speed TSPC (E-TSPC) flip-flop was employed to guarantee adequate design margin, which reduces one MOS transistor stack compared with the traditional TSPC design. Despite an increase in static power consumption, the circuit speed is subsequently improved. Moreover, the high-speed TSPC flip-flop can reduce the number of logic gates in the dual-modulus prescaler by incorporating “AND” logic into its structure.
Phase-frequency detector
In modern phase-locked loop designs, the commonly used frequency and phase detector is generally based on D flip-flops. The detailed structure of the phase-frequency detector (PFD) is shown in Fig. 3h, which consists of two D flip-flops, inverters, the transmission gates that make up the buffer stage, and an AND gate in the reset path. The phase frequency detector employed in the current design offers a wide phase detection range and is featured with a simple circuit design. The delay of the reset path is 600 ps at 4 K and thus the minimum pulse of PFD can fully turn on the switches in the charge pump to eliminate the dead zone. Besides, to ensure that the digital differential signal with sufficient driving capability matches the charge pump circuit, a buffer circuit composed of transmission gates and inverters is connected after the PFD. The buffer circuit generates four signals, namely UP, UPB, DN, and DNB, which serve as input signals for the current steering charge pump.
MEASUREMENT RESULTS
The cryogenic clock generator was fabricated in a standard 180 nm bulk CMOS process. The micrograph of the clock generator is shown in Fig. 4a and the overall area without pads is ∼415 × 593 µm2. Fig. 4b shows the cryogenic measurement setup and the chip was wire-bonded to PCB and placed in a Lakeshore 4 K cryogenic probe station. Besides, C0G- (NP0-)type capacitors, dry tantalum capacitors, and thin film resistors were employed on the low-temperature PCB due to the fact that they perform relatively stable over a wide temperature range53. The chip power was applied and the output signal was detected via the cryogenic probes (Fig. 4c). Low-dropout regulators (LDOs) commonly adopt a bandgap voltage reference. However, the bandgap reference is unusable due to the failure of BJTs. Therefore, a separate PCB board was employed to solder the test LDOs, which is then connected to the chip test board via coaxial cables. The reference clock was provided by the signal generator and the output signal is observed through an oscilloscope. The signal was also fed into a signal analyzer (Keysight N9030B) so as to obtain the spectrum and phase noise curve.
Fig. 4. Details of measurement. a, Chip micrograph. b, Cryogenic measurement setup. c, Cryogenic PCB in the probe station. Design of loop filter parameters for d, room temperature and e, 4 K conditions. The measurement and simulation results of the F-V curves of the VCO at f, 300 K and g, 4 K. |
Before the overall test begins, it is necessary to perform a separate test on the VCO. At room temperature, the VCO exhibits a frequency coverage range of ∼230 to 575 MHz within the control voltage range of 0.75 to 1.8 V, and the frequency can exceed 600 MHz when the control voltage is close to 0. Under the output frequency of 232 MHz, the phase noise at 1 MHz frequency offset is −116.12 dBc/Hz, while when the output frequency is set at 612 MHz, the phase noise at 1 MHz frequency offset is −113.82 dBc/Hz. At 4 K, the VCO covers a frequency range of ∼330 to 900 MHz within the control voltage range of 0.75 to 1.8 V. The phase noise curve of the VCO is shown for two different frequencies: 359 MHz and 881 MHz. At 359 MHz, the phase noise at 1 MHz offset is −104.08 dBc/Hz, and at 881 MHz, it is −105.9 dBc/Hz at 1 MHz offset.
The loop filter is a third-order passive structure with the adoption of external resistors and capacitors. According to the frequency-to-voltage (F-V) curve of the VCO, the tuning gain Kvco of the VCO at room temperature is ∼360 MHz/V and ∼700 MHz/V at 4 K, respectively. Combined with other loop parameters such as the loop bandwidth and charge pump current, the calculated parameters of each component in the loop filter are shown in Fig. 4d and Fig. 4e. The measurement and simulation results of the F-V curves of the VCO are shown in Fig. 4f and Fig. 4g, respectively. At 300 K, the measurement results are in good agreement with the simulation results. At 4 K, although the trend of the F-V curve is consistent, there exists a deviation between measurement and simulation results, especially at high frequencies. As discussed in the modeling section, this deviation can be attributed to the absence of parasitic capacitance correction in the cryo-CMOS model, which is important for high-frequency circuit designs.
The performance measurement results of the clock generator at 300 K and 4 K are listed in Table 2 and Table 3, respectively. When the clock generator is running at the target frequency (600 MHz), the measured spectrum and phase noise of 300 K and 4 K are shown in Fig. 5. The clock generator's 600 MHz output spectrum at room temperature is shown in Fig. 5a, with a reference spur of −63.16 dBc. The phase noise curve is shown in Fig. 5b, with in-band phase noise of −89.68 dBc/Hz @10 kHz and out-of-band phase noise of −112.01 dBc/Hz @1 MHz. The RMS jitter is calculated to be ∼9.1 ps (12 kHz to 20 MHz) based on the integrated phase noise curve.
Table 2. Performance of clock generator with different output frequencies at 300 K. |
| Output frequency (MHz) | Reference spur (dBc) | Phase noise @10 kHz (dBc/Hz) | Phase noise @1 MHz (dBc/Hz) |
|---|---|---|---|
| 300 | −38.84 | −94.47 | −108.4 |
| 400 | −35.94 | −91.57 | −88.19 |
| 500 | −42.33 | −96.17 | −105.21 |
| 600 | −63.16 | −89.68 | −112.01 |
Table 3. Performance of clock generator with different output frequencies at 4 K. |
| Output frequency (MHz) | Reference spur (dBc) | Phase noise @10 kHz (dBc/Hz) | Phase noise @1 MHz (dBc/Hz) |
|---|---|---|---|
| 450 | −38.16 | −94.18 | −96.53 |
| 550 | −32.44 | −97.09 | −103.88 |
| 600 | −39.32 | −95.53 | −102.73 |
| 650 | −32.5 | −95.56 | −102.37 |
| 750 | −48.15 | −96.41 | −109.27 |
| 850 | −34.61 | −74.41 | −114.72 |
Fig. 5. Measured spectrum and phase noise of the PLL. a, Measured spectrum when the clock generator is running at 600 MHz at 300 K. b, Measured phase noise plot when the clock generator is running at 600 MHz at 300 K. c, Measured spectrum when the clock generator is running at 600 MHz at 4 K. d, Measured phase noise plot when the clock generator is running at 600 MHz at 4 K. |
The 600 MHz output spectrum of the clock generator at 4 K is shown in Fig. 5c, with a reference spur of approximately −39.32 dBc. As shown in Fig. 5d, the phase noise of the clock generator is −95.53 dBc/Hz, −97.07 dBc/Hz, and −102.73 dBc/Hz at 10 kHz, 100 kHz, and 1 MHz frequency offset, respectively. And the RMS jitter is < 4.8 ps between 12 kHz and 20 MHz, which is corresponding to a jitter-power FOM of −211.6 dB. Table 4 shows the detailed performance comparison of the presented PLL. At such a low temperature, i.e. 4 K, the proposed technique still exhibits good performance, which could be potentially used as a clock generator for ADCs and DACs in the qubit-interfaced cryo-CMOS controllers.
Table 4. Benchmark with other works. |
| Specifications | JSSC 202254 | ASSCC 201955 | ISSCC 202256 | ASSCC 202057 | This work |
|---|---|---|---|---|---|
| Temperature (K) | 3.5 | 300 | 3.5 | 300 | 4 |
| Topology | LC + CPPLL | Ring + CPPLL | LC + DPLL | Ring + CPPLL | Ring + CPPLL |
| Technology (nm) | 40 | 65 | 40 | 110 | 180 |
| Power supply (V) | N/A | 1 | 1 | 3.3/1.5 | 1.8 |
| FPLL (GHz) | 12.7 | 0.432 | 11.392 | 1.6125 | 0.6 |
| FTR (GHz) | 10.8 to 17.3 | 0.36 to 0.456 | 9 to 13 | 0.4 to 1.7 | 0.45 to 0.85 |
| Fref (MHz) | 50.4 | 24 | 356 | 25 | 20 |
| PN@1 MHz (dBc/Hz) | −115 | −98.9 | N/A | −100.8 | −102.7 |
| RMS jitter (ps) [Int.Bandwidth] | N/A | N/A | 0.274 | 3.78 | 4.8 |
| [N/A] | [100 to 40 MHz] | [12 k to 20 MHz] | |||
| Spur (dBc) | −55.6 | −68.9 | N/A | NA | −39.32 |
| Area (mm2) | N/A | 0.064 | 0.068 | 0.284 | 0.246 |
| Power consumption (mW) | 11.15 | 1.11 | 12.5 | 21.1 | 30 (with test buffer) |
| FOMa (dB) | N/A | −218.7 | −240.3 | −215.2 | −211.6 |
aFoM=10lg[(JRMS1s)2·Power1mW]. |
CONCLUSIONS
This work presents the characterization and modeling of commercial 180 nm CMOS transistors down to 4 K. Based on the proposed model, a 180 nm process clock generator for the control and read-out electronics of qubits is presented. At 300 K with a 600 MHz output frequency, the clock generator achieves a phase noise of −89.68 dBc/Hz at 10 kHz offset, and −102.73 dBc/Hz at 1 MHz offset. At 4 K, the clock generator exhibits an output frequency range of 450 to 850 MHz. When the output frequency is set to 600 MHz, a phase noise of −95.53 dBc/Hz at 10 kHz offset, −112.01 dBc/Hz at 1 MHz offset, and < 4.8 ps RMS jitter, −39.32 dBc reference spur with 30 mW power consumption (with test buffer) were achieved, which is corresponding to a jitter-power FOM of −211.6 dB. Endowed with the demonstrated performance, this clock generator could provide a stable local clock signal for AD/DA or digital circuits at cryogenic temperatures in large-scale quantum processors.
MISCELLANEA
Acknowledgments The authors gratefully acknowledge the support from the National Natural Science Foundation of China (No. 12034018) and the Innovation Program for Quantum Science and Technology (No. 2021ZD0302300).
Declaration of Competing Interest The authors declare no competing interests.
