INTRODUCTION
An ingenious use of the laws of quantum mechanics has led to a new computing paradigm, generally known as quantum computing, that promises exponential speed-up in the solution of certain types of problems1, 2, 3. With the adoption of a prototypical quantum processor with 53 operational superconducting quantum bits (qubits), a first ground-breaking experiment was performed to investigate quantum supremancy4, triggering more extensive researches on such a goal5. Practical implementations of quantum computing, however, are expected to require much larger numbers of physical qubits6.
Solid-state implementations seem to offer the best scalability prospects. While superconducting qubits are currently the leading platform, complemtary metal-oxide-semiconductor (CMOS) spin qubits are emerging as a serious contender owing to the possibility to leverage the integration capabilities of silicon technology7. Very recently, promising developments of spin qubits in Si/Ge heterostructures have reached the level of a quantum processor of up to 6 qubits8,9. For both superconducting and semiconducting qubits, the quantum processor functions at very low temperature, typically below 0.1 K, but it has recently been shown that silicon qubits can be operated even above 1 K with limited loss of fidelity10,11.
In the quest to scale up to larger numbers of qubits, the use of classical cryogenic electronics positioned as close as possible to the qubits is widely considered a necessity12,13. Various transistor building blocks have been demonstrated at low temperatures to prove their feasibility. These include (de)multiplexers14,15, analog-to-digital and digital-to-analog converters16, 17, 18, 19, low-noise amplifiers20,21, RF oscillators22,23, and transimpedance amplifiers24,25. More elaborated circuits involving radio frequency (RF) arbitrary wave generators have been developed for high-fidelity qubit control, which operate at ∼4 K for reasons of cooling power26, 27, 28, 29, 30. CMOS-based cryogenic controllers operating at ∼4 K were reported to enable high-fidelity operations on Si electron-spin qubits31 and on superconducting qubits32. In an even more complete approach of the controller, qubit-readout components have been added to the cryogenic circuit33,34. In a random-access strategy with microwave multiplexing of qubits35,36, these cryogenic controllers can significantly reduce the number of electrical lines running through the host cryostat, thereby limiting the associated heat load.
Measuring the qubit state involves the detection of small capacitance variations in the impedance of an LC tank circuit coupled to the qubit, which is commonly completed through RF reflectometry. The inductive element of this tank circuit is typically made up of a surface-mount inductor or a microfabricated superconducting coil. Even for this second case, the corresponding footprint is relatively large (∼mm2) compared to the qubit size (∼100 nm) and is hence hardly compatible with large-scale qubit integration.
In the current work, an alternative readout technique called impedancemetry was adopted for measuring the impedance of the LC tank at resonance, which in our case is around 200 MHz. Unlike the reflectometry method based on traveling wave analysis where 50 Ω impedance matching plays a crucial role in achieving the optimal sensitivity, the proposed impedancemetry method relies on the direct impedance measurement of a resonant circuit which contains the capacitance to be measured through the locally applied currents and detected voltages. As an essential difference with reflectometry, the sensitivity of impedancemetry depends much less on the 50 Ω matching criterion for the measured value of the impedance of the resonant circuit.
In order to minimize the surface of the cryogenic readout circuit, a CMOS-based active inductor was adopted in the LC resonator. The reduced footprint of the CMOS inductor allows for scalability and enables adjustments of the characteristic frequency and quality factor of the resonator, which is crucial for optimizing measurement sensitivity in terms of signal-to-noise ratio (SNR). Besides the performance of the active inductor in terms of noise, the power consumption also forms an important issue in the evaluation of the proposed cryogenic CMOS inductor. The circuit is completed with an RF current source exciting the LC tank containing the capacitor of the device under test (DUT) and an amplifier to read the voltage response of the resonator. The circuit sensitivity and tunability was characterized at 4.2 K with an addressable capacitor bank demonstrating its capability to measure capacitances as low as 10 aF. Finally, the proposed approach has enabled in situ impedancemetry measurements of the capacitance of individually addressed gate-coupled transistors. The observed oscillatory signals in the gate capacitance demonstrate the capability to measure quantum phenomena with an on-chip resonator composed of active inductance and nanometric transistors.
IMPEDANCEMETRY
As shown in Fig. 1, capacitive spectroscopy of gate-controlled quantum-dot devices allows the detection of electronic quantum states within the structure, including the firstly occupied electron states. For enhanced detection sensitivity at high speed, the gate capacitance of the DUT, which is represented as a single-electron transistor in Fig. 1b, is connected to an inductance to form an LC resonator. In a gate-coupled readout scheme of the quantum state, the response of the tank at cryogenic temperature excited near resonance frequency fr is usually probed and analyzed at room temperature with homodyne I-Q detection. The phase change Δφ of the tank response tends to be an image of the change in DUT capacitance ΔC ≪ Cp (see Fig. 1a) through the relation Δφ = QΔC/Cp around fr with the resonator quality factor of Q and the parallel (parasitic) capacitance of Cp.
Fig. 1. Integration of measuring circuitry for readout of quantum capacitance. a, Schematic signals of amplitude and phase for the complex scattering coefficient S11 and impedance Zr of a resonant circuit in, respectively, reflectometry and impedancemetry. b, Comparison between a typical reflectometry setup (left) and the proposed impedancemetry setup (right) for the measurement of the quantum capacitance Cq of a single-electron transistor embedded in a resonant LC circuit. Impedancemetry with the integrated cryogenic electronics for applied current Iin and amplified signal IinZr leads to a lower footprint of the measurement circuitry by getting rid of bulky directional couplers. Red (respectively green) arrows represent voltages (resp. currents). Red-green arrows emphasize the voltage-current interdependence due to signal propagation in 50-Ω lines. |
Fig. 1b shows a schematic comparison of qubit resonance experiments between reflectometry and the newly proposed method of impedancemetry. The commonly adopted reflectometry utilized voltages to excite and probe the resonator via the scattering37r transmission38f the propagating waves. Directional couplers or circulators are employed to isolate the incoming and outgoing signals.
The impedancemetry approach for qubit detection adopts currents to excite the resonator and measures the impedance without the requirement of bulky RF elements. The incoming signal Vin at the resonant frequency fr, which is generated at room temperature, is converted into a current Iin = GmVin with a voltage-controlled current source of transimpedance Gm at the base temperature. The input current Iin creates a voltage Vout = ZrIin through the tank impedance Zr that carries the information about the DUT capacitance. Vout is conveyed to a low-power unity-gain amplifier (follower), which should be placed as close to the DUT as possible so as to reduce parasitic capacitance Cpar. Typically, the main amplification is placed at higher temperature (typically 4.2 K) to benefit from higher cooling power. Note that, compared to the schematic layout of Fig. 1b with the DUT at sub-Kelvin temperatures, the resonator and DUT of the realized circuit are all on-chip, together with current excitation and amplification stage for the impedancemetry measurements performed at 4.2 K.
Impedancemetry shows the advantage over reflectometry that the 50 Ω impedance matching plays no role in the optimization of the resonant circuit depending on the inductor and the parallel (parasitic) capacitors. However, the cryogenic circuitry required by impedancemetry generates extra noise compared to reflectometry, which needs to be minimized. The impedance of the resonator naturally filters out-of-resonance components (see Fig. 1a) such as low-frequency flicker noise from electronics. In the perspective of quantum computing involving a qubit matrix, Vin could contain a comb of excitation frequencies to excite a set of frequency-selective resonators.
In the Supplementary Material I, a comparison is made between reflectometry and impedancemetry with respect to the scaling with the number of qubits for a N × N array. The footprint of the reflectometry circuit is dominated by the directional coupler occupying approximately 1 cm2 (for frequencies below a few GHz), which in the transmission variant of reflectometry would be replaced by the doubled footprint of the input and output connectors (0.1 cm2). A passive micro-Henry inductance, which is about 1 mm2 (below a few GHz), would dominate the footprint of the impedancemetry circuit.
The connection fan-out of a qubit matrix, which is originated from objects of different scales, increases the average interconnection length and thus lowers the detection sensitivity with important parasitic capacitance. The applied high magnetic field (∼1 T) required to separate spin states via the Zeeman effect prevents an effective use of ferrite materials for reducing the inductance size.
The chosen implementation of an active inductance consisting of transistors and capacitors enables an inductance density as high as a few mH/mm2, which is 3 to 4 orders of magnitude higher than that of passive inductances. In addition, active inductances couple only capacitively to each other, allowing for an even denser layout in large-scale implementations. On the contrary, passive inductances couple magnetically over a longer range, which can be more challenging to deal with than capacitive interactions. In the following sections, the realized active inductance will be treated in relation to sensitive capacitance detection while taking the important issues of dissipation and noise into consideration.
ACTIVE INDUCTANCE
The active inductance behavior is realized by transforming a capacitor CL into an inductance L = CL/Gm,1Gm,2 via two transistor devices of transimpedance Gm,1 and Gm,2, thus forming a gyrator39. The non-ideal finite conductance and parasitic capacitance of the transistors set the resonant frequency fr and quality factor Q. More advanced active inductance architectures incorporate a negative resistor in parallel to the inductance, which thus improves Q up to a few hundreds with independent tuning of the inductance value L and the quality factor Q39,40.
Fine calibration of the tunable inductance value with the adoption of a capacitor bank leads to a precise definition of the resonant frequency value, which is ideal for the optimal frequency-multiplexing of large qubit matrices. The tunability of the Q factor enables different modes of readout. High Q gives a precise measurement of quantum capacitance to calibrate qubit matrices. Lower Q is more suitable for fast readout during quantum computation.
INTEGRATED CIRCUIT DESIGN
The impedancemetry experiment was integrated on a single chip with multiplexed quantum devices with the adoption of the Fully-Depleted Silicon-On-Insulator (FD-SOI) 28 nm CMOS technology. The FD-SOI technology is ideal for for high-speed cryogenic applications41 with lower variability than bulk technologies42, less sensitivity to carrier freeze-out, and threshold-voltage tuning via the back gate43. The integration of classical circuitry with small-enough transistors that exhibit quantum properties is a plus to efficiently validate new circuit architectures22,25,44.
The realized integrated circuit contains the current source, the active inductance with addressable capacitor banks for tunability, the multiplexed DUTs, and the amplification stage (Fig. 2a and b). During design, emphasis was laid upon bringing down the footprint and power consumption of the active inductance, which is the main original component of our circuit. The current generation and voltage-signal amplification were added on-chip to facilitate testing the concept of impedancemetry at 4.2 K. In the absence of high-frequency models of FD-SOI transistors at cryogenic temperatures, the integrated circuit was designed with accurate room-temperature models supplied by the foundry45. The evolution of transistor characteristics towards the lowest temperature was extrapolated not only from the temperature variation in foundry models but also from the acquired 4.2 K data of single transistors42,43. The chosen implementation for the general design of the complete impedancemetry chip can be found in the Supplementary Material II.
Fig. 2. Setup with on-chip electronics. a, On-chip circuit implementation of the active inductance (pink), current excitation (green), test capacitor bank (blue), and amplification stage (red). For clarity, the bias MOSFETs operating under DC are drawn of smaller size than MOSFETs in the high-frequency signal chain. b, Simplified view of the on-chip resonant circuit placed at 4.2 K with tunable resonator, DUT, current excitation, and voltage amplification, linked to room-temperature phase-sensitive electronics via meter-long cables. c, Room-temperature homodyne detection with single (I) and double (II) demodulation of the circuit output Vout and generation of voltage excitation Vin at modulation frequencies f1 (150-200 MHz) and f2 (1 kHz). Abbreviations: MOSFET = metal-oxide-semiconductor field-effect transistor; DUT = device under test; DC = direct current. |
The active inductance follows a known n-type metal-oxide semiconductor-based Karsilayan-Schaumann architecture46,47. The gyrator is made of a single-ended negative transconductance −Gm,1 and a differential transconductance stage Gm,2, which are coupled to a tunable capacitance CL and lead to a tunable inductance L(CL) = CL/Gm,1Gm,2. An added metal-oxide-metal (MOM) capacitor Cp of 136 fF parallel to L controls the resonant frequency . No dependence in temperature is expected for MOM capacitors48. Adding Cp makes the measuring circuit less sensitive to a change in the DUT-capacitance with the increased tank capacitance, which whereas avoids the influence of unknown parasitic circuit capacitances. Hence, the resonant frequency fr is set by Cp, CL, and Gm,i = 1,2. CL is implemented with one main MOM capacitor of 362 fF in parallel with two digitally controlled binary weighted MOM capacitors of 68 and 136 fF (see Supplementary Material II).
Adding a capacitance CR at the foot of the differential transconductance stage allows the introduction of a negative resistance in series with the active inductance, leading to a higher Q-factor with an increased effective parallel resistance R(CR, CL). The Q factor of the active inductance defined as depends on CL and CR. By tuning CL and then CR, L and Q can be adjusted to any desired value apart from possible instabilities. In order to tune the Q factor, a wide range of CR values were covered in steps of 23 fF by selecting 4 binary-weighted MOM capacitors of 23, 46, 92 and 184 fF.
The voltage-controlled current source exciting the resonator is made of a current mirror combined to an RC bias tee. The bias tee superimposes the direct current (DC) signals from the diode transistor, which sets the DC operating point of the current source and alternating current signals from the excitation input Vin and thus facilitates the generatation of the alternating current Iin. The RC filter of the bias tee is composed of Rbt (non-silicided polysilicon resistor of 10 MΩ) and Cbt (MOM capacitor of 406 fF), reaching a characteristic frequency of 39 kHz. As no large signals Vin are required, the current source operates in subthreshold regime with a bias current of only 0.1 μA, thus minimizing its conductance for a negligible impact on the resonator and achieving a desirable low transconductance for nA current excitation.
In order to investigate the active inductance circuit with different DUTs, an addressable bank of 6 capacitors (Supplementary Material II) was added. Three MOM capacitors of 2, 4, and 8 fF play the role of calibrating the active inductance on known values. Three additional metal-oxide-semiconductor field-effect transistors (MOSFETs) (M0, M1, M2) with the width of 80 nm and the length of 28, 60, and 120 nm are used as test bench for the investigation of quantum properties. The source and drain voltages of the quantum MOSFETs were grounded when unselected, while they were polarized at Vbias when selected. The differential transconductance stage of the active inductance copies the DC common-mode voltage Vcm to the DUT gate potential, so that the DC gate voltage Vgs = Vcm − Vbias can be varied via Vbias (see Fig. 2).
Once excited by Iin, the tank voltage is amplified and subsequently sent through a unit-gain buffer for detection at room temperature via meter-long cable. The amplifier is a common-source n-type single-stage one, and the 1 : 1 buffer is a common-drain n-type single-stage one (see Fig. 2a).
The specifications of the circuit at room temperature, including inductance values, resonance frequencies, Q-factors, power consumption and amplifier characteristics, have been extracted from simulations with the adoption of foundry models (see Supplementary Material III for more details). The emulated inductance L ranges from 5.3 to 8.4 μH to reach a resonance frequency fr from 128 to 165 MHz. The settings of tuning CL and CR allow covering a wide range of quality factors Q from 7 to 300, along with the occurrence of negative Q values that lead to instabilities. The estimated power consumption of the resonator is 85 μW, which could be shared among a number of qubits in a frequency-multiplexed array depending on the allowed frequency spacing within the bandwidth.
From the foundry models at room temperature, a transconductance Gm of 3.4 nA/mV with a bandwidth of 3.5 GHz was achieved for the current-generating transisto (see Supplementary Material III). The first amplifier stage exhibits a gain A of 15 dB and a bandwidth of 1.8 GHz for a power consumption of 150 μW. The next buffer stage in the amplification reaches a bandwidth of 92 MHz for a cable capacitance of 50 pF and a power consumption of 2.4 mW. The net amplification at 165 MHz tends to be 8 dB.
Transistor noise was translated into transconductance noise for the transistors, thus forming the gyrator-like inductance circuit, which generates perturbing variations of the active inductance. A varying L modulates fr and generates phase noise in Vout. The phase noise spectrum of Vout around the carrier frequency fr extracted from room-temperature steady-state simulations exhibits a 1/f-flicker component (see Supplementary Material III) on time scales larger than 10 ms, which is resulted from a noisy L. For a typical Q of 81 with sufficiently fast measurements at frequencies above 100 Hz to avoid 1/f noise, this is translated into a phase noise of 0.002°/ and thus leads to an input-referred noise of 3.2 aF/. This estimated noise in measured capacitance can be compared with the lower and upper ranges (roughly from 10 aF to 1 fF) of the quantum capacitance in a semiconductor qubit, which would require a noise level of 0.003 to 0.3 aF/ for 99% readout fidelity (or SNR = 22) in 1 μs (see Eqs. 17 to 19 in ref.49). While the noise of the designed impedancemetry circuit may be too large for fast single-shot qubit-state detection with high fidelity, the noise performance could be improved in the future by optimizing the active inductor architecture and taking advantage of forthcoming compact transistor models at cryogenic temperatures.
Voltage excitation and homodyne detection were performed at room temperature with an all-digital lock-in amplifier (Fig. 2c). Different configurations for single (I) and double (II a, b) demodulation are further described in the following section when needed.
IMPEDANCEMETRY CIRCUIT CHARACTERIZATION
Without the assistance of low-temperature models, the operating point of the circuit needs to be determined experimentally starting from room-temperature settings of bias voltages and currents. The increase in threshold voltage of n-type metal-oxide-semiconductor (resp. p-type metal-oxide-semiconductor) transistors at 4.2 K is compensated by applying a back-gate voltage of 1.2 V (resp. −2 V). The optimal cryogenic common-mode voltage Vcm = 0.48 V was obtained while monitoring the tank impedance via repeated frequency sweeps until a typical resonance behavior up to 200 MHz emerges for the lowest values of CL and CR. The gain of the low-temperature amplification stage at fr is optimized with respect to the current bias of amplifier and buffer (see Supplementary Material IV for a detailed low-temperature characterization of the amplifiers). The main results of the impedancemetry with respect to tunability and detection sensitivity are shown in Fig. 3.
Fig. 3. Characterization of the resonant circuit at 4.2 K for capacitance detection. a, Amplitude and phase of the demodulated circuit output Vout for several active inductance settings. The resonance frequency shifts to lower frequency as the inductance value increases with increasing CL (different colors). The continuous line (low-Q) and dashed line (high-Q) show the signals for different values of CR. b, Data points for the resonance frequency fr when the extracted Q is tuned with CR. The colored bars of width given by the written maximal deviation indicate the low dispersion of fr for fixed CL when varying Q with CR. c, Measured phase shift for MOM capacitor Cm of 2, 4, and 8 fF in several Q factor settings. The capacitance sensitivity Δφ/Cm of the circuit is extracted from the slope with a least square fit at given Q. d, Capacitance sensitivity extracted from c as a function of the Q factor. A least square linear fit of Δφ/Cm(Q) allows the extraction of the capacitance Cp parallel with the active inductance. Abbreviations: MOM = metal-oxide-metal. |
The amplitude and phase of Vout with the adoption of single homodyne detection (I) without any connected DUT are shown in Fig. 3a for the 4 CL values from 362 to 566 fF, and two CR values chosen between 0 and 322 fF depending on CL. Vout at maximal amplitude were kept equal to 1.8 mV by adjusting Vin to avoid non-linearities coming from non-linear MOSFETs’ behavior. The resonance frequency fr varies by 5% from 189 to 199 MHz by tuning CL. The quality factors Q extracted from a linear fit of the phase around fr are shown in Fig. 3b. The Q values range from 80 to 250 and can be tuned by a factor >2 for every CL by adjusting CR. These data demonstrate that Q can be tuned almost independently of the resonance frequency, with a frequency variation of less than 0.22% across the entire CR range (see Fig. 3b).
For the minimum value of CL with the highest resonance frequency, the capacitance sensitivity of the circuit was calibrated for each Q by switching on and off the DUT MOM capacitors Cm = 2, 3, and 8 fF and using double homodyne detection (II a) (see Fig. 3c). The capacitance sensitivity α is extracted from a least-square linear fit of the phase change Δφ = QCm/Cp ≡ αCm for a given Q as shown in Fig. 3d. The sensitivity α increases linearly with Q from 0.76 to 1.9°/fF. From the linear fit in Fig. 3d, Cp = 137 fF was achieved, which is in good agreement with the designed value (136 fF). In usual circuits without an additional input capacitance46, the parasitic capacitance of the MOSFETs determines the resonance frequency. In future design with accurate cryogenic compact models, this capacitance can be reduced significantly, which leads to a higher resonance frequency and improved sensitivity, along with larger Q.
From Cp and fr, the inductance value L can be deduced. By adjusting CL, L varies from 2.42 to 5.18 μH. For a total footprint of 60 × 50 μm, the active inductance density of 1.73 mH/mm2 is five orders of magnitude higher than that of the previously used passive inductors (55 nH/mm2)37 and three orders of magnitude higher than that of the superconducting inductors (1.6 μH/mm2)50.
From the bias-current settings at cryogenic temperatures, a reliable estimate of the power consumption of the impedancemetry circuit can be given, at low temperatures amounting to 123 μW for the active inductance, 0.15 μW for the input-current source, and 2.9 mW for the output amplification. These values can be reasonably compared with the circuit simulation at ambient temperature mentioned previously.
CAPACITANCE RESOLUTION
We will now examine the capacitance resolution of the setup in deriving the input-referred noise in aF/Hz from the SNR as a function of the integration time tint.
To accomplish this, a capacitance change is generated by continuously connecting and disconnecting the DUT MOM capacitor Cm = 2 fF at a rate of 1 kHz. With the adoption of the demodulation method (I), the square wave of the phase φ at fr with a rise time given by the integration time is used to extract the signal power Psig and noise power Pnoise by separating the corresponding frequency components in the power spectrum (see Supplementary Material IV for the used method of analysis). The resulting SNR = Psig/Pnoise is used to extract the capacitance resolution given by the equivalent Cm(SNR = 1) = Cm/SNR shown in Fig. 4 as a function of tint from 100 ns to 100 μs. A capacitance of 1 fF can be detected with an integration time of 1 μs with SNR = 1. The capacitance resolution follows a square-root law with tint, from which the equivalent input-referred noise of 3.7 aF/ can be extracted, which is close to the previously mentioned noise extracted from room-temperature simulations. The obtained noise amplitude is two orders of magnitude higher than the best-reported sensitivity using an ultra-low noise SQUID amplifier (0.07 aF/)51. However, removing the SQUID amplifier and only measuring with the remaining standard 4-K semiconductor amplifier increases the noise to 1.6 aF/51, which lies in the same order of magnitude as the obtained noise for our approach.
Fig. 4. Capacitance resolution of the measurement setup at 4.2 K. Extrapolated capacitance Cm at a signal-to-noise ratio equal to 1 for single (I) (black circles) and double (IIa) (red squares) homodyne detection of the capacitance measurement as a function of the integration time tint. Dashed lines are least-square fits with and Sc (indicated values) being the equivalent noise spectral density in aF/ of the capacitance measurement. |
A correlated noise of the type of a two-level fluctuator appears on longer time scales, which is probably originated from the 1/f flicker noise of the transistors, preventing measurements at times longer than 1 ms with the adoption of the detection method (I). To remove the phase noise originating from the fluctuating L, a second demodulation (IIa) was added at the capacitance switching frequency of 1 kHz. The 1 kHz square wave φ from (I) with an integration time of 100 μs was demodulated by method (IIa) at 1 kHz so as to obtain its amplitude |φ|. The capacitance resolution as a function of the second integration time for the 1-kHz demodulation was extracted by taking the ratio of the average and the standard deviation of the |φ| signal, as is shown in Fig. 4. With an integration time of 1 s, the experimentally observed resolution tends to be as low as 10 aF.
QUANTUM CAPACITANCE MEASUREMENTS
With the calibrated impedancemetry circuit, we are able to detect the gate quantum capacitance Cgg of the multiplexed tiny MOSFETs (M0, M1, and M2 in Fig. 2a) similar to the ones used to implement spin qubits with CMOS technology7. Measurements will be presented for M2 with a gate length of 120 nm and a gate width of 80 nm. The device M1 with the length of 60 nm and the width of 80 nm shows similar behavior (see Supplementary Material V). The device M0 with the length of 28 nm and the width of 80 nm did not reveal any distinct oscillatory structure above the noise level as observed in the other two devices.
The total gate capacitance Cgg of such devices corresponds to the sum of the capacitance to drain, source, back-gate, and MOSFET channel of which the gate to channel capacitance depends highly on the gate-source voltage Vgs controlled by the DC component of Vbias via the equation Vgs = Vcm − Vbias (see Fig. 2a). As Cgg of a nanometric device (few aF) is extremely small compared to Cp = 136 fF, it is not expected to have sufficient SNR for small capacitance variations at reasonable integration times. Better sensitivity can be obtained by modulating Vgs (method IIb) to measure after demodulation the first derivative dCgg/dVgs as Cgg varies a lot in a small Vgs window.
While the resonator impedance is probed at 199 MHz, Vgs is modulated at 1 kHz with an mV-range excitation on Vbias (see Fig. 2b and c). The obtained result with a relatively large 25 mV Vgs modulation (shown in Fig. 5a) is reminiscent of the typical gate capacitance variation around threshold voltage Vth ≃ 0 V shown for Vbg = 6 V. Cgg (see inset of Fig. 5a) reflects the typical behavior for a field-effect transistor capacitance from the subthreshold regime Vgs ≪ Vth to the strong inversion regime Vgs ≫ Vth. As shown in the inset of Fig. 5a, the measured overall change in gate capacitance is approximately 6 aF, which could be compared with the expected geometric capacitance of 77 aF for M1, using a crude parallel-plate approximation with transistor gate area and a 1.1 nm-equivalent silicon-oxide thickness for GO1 transistor devices. The circuit in series with the gate capacitance, which is used to apply the gate voltage (see Fig. S5b and c in Supplementary Material II), might play a role to explain the discrepancy between the measured DUT capacitance and the expected value for small values of capacitance.
Fig. 5. Quantum capacitance measurement of an integrated MOSFET with a channel length of 120 nm and a width of 80 nm at 4.2 K. a, Measurement of the first derivative of the gate capacitance Cgg with respect to Vgs by applying a gate-source AC excitation of 25 mV. The inset shows the capacitance Cgg(Vgs) variation of approximately 6 aF near threshold gate voltage computed from the integrated signal of the derivative, to be compared with the geometric gate capacitance for this MOSFET (see text). b, Expanded view of dCgg/dVgs around the off-on transition of the MOSFET measured with a smaller excitation of 3.1 mV. The resolved features are signatures of quantized electronic states in the measured capacitance of the MOSFET channel. c, Evolution of dCgg/dVgs with the back-gate voltage Vbg and the gate-source voltage Vgs. The indicated slopes β = dVbg/dVgs ≃ Cg−ch/Cbg−ch represent the relative coupling strength of the detected quantized states with respect to back gate and front gate. Abbreviations: AC = alternating current; MOSFET = metal-oxide-semiconductor field-effect transistor. |
Upon decreasing the amplitude of the Vgs modulation to only 3.1 mV, the observed dCgg/dVgs signal in Fig. 5b reveals a fine structure around Vth, which is composed of successive peak-dip oscillations. Following numerical integration, these features result in a series of peaks in Cgg, which can be interpreted as quantum contributions to the capacitance coming from electrons tunneling in and out of randomly localized quantum states within the transistor channel. Such quantum phenomena have been observed previously in various CMOS devices (see review52), including nanometer-sized transistor channels made of the same FD-SOI 28 nm technology43.
To further identify these quantum states, dCgg/dVgs for different back-gate voltage Vbg was acquired from 2 to 6 V, as shown in Fig. 5c. As Vbg increases, all the observed features shift to lower Vgs with a slope close to the ratio β = Cg−ch/Cbg−ch of the gate-channel capacitance Cg−ch over the back-gate-channel capacitance Cbg−ch alike the Vth-shift with back-gate for similar field-effect transistor devices43. For Vbg > 4V > 4 V, all features exhibit a coupling ratio of 10 except for one with a lower coupling of 8.6, which is attributed to an impurity closer to the back-gate interface. No anomalous impurity structure is detected in the smaller 60 × 80 nm device (see Supplementary Material V). At lower Vbg, the coupling increases with rising Vgs from 10 to 14 as the electron-filled inversion layer is brought back to the top interface. The systematic gate-voltage variation of the oscillatory structures with applied back-gate voltage gives additional evidence that these structures are resulted from the DUT transistor.
While there is still room for improvement in the noise of the active inductor and the power consumption of the amplifier stages, these measurements demonstrate that the proposed integrated impedancemetry approach can detect the capacitive signatures of structure in the electronic density of states of quantum dots.
CONCLUSIONS
The current work reported an integrated circuit that performs impedancemetry of a resonator coupled to a quantum dot for the measurement of quantum capacitance at cryogenic temperatures. The realized on-chip circuit of the impedance meter operating at 4.2 K allows the measurement of quantum capacitance with a resolution down to 10 aF (noise level 3.7 aF/). Although further improvements should be made in the noise performance so as to be competitive with state-of-the-art reflectometry on quantum devices, the implementation of the active inductance in the resonator enabled the controlled tuning of the resonance frequency and quality factor, which will be of great importance for the optimal frequency-spectrum crowding in multiplexed readout schemes. Novel readout architectures with cryogenic electronics, such as the active inductance with its much smaller footprint compared to passive circuit elements, show great potential to increase scalability and flexibility in the design and exploitation of quantum processors.
The time multiplexing of nanometric quantum devices with on-chip switches can be beneficial for reducing the power consumption per qubit in a scalable multi-qubit architecture. Combined with frequency multiplexing, the dissipated power of about 100 μW for the resonator circuit could be used for the readout of 100 or more qubits by optimizing the frequency bandwidth and resolution. In order to improve the impedancemetry method, the amplification stages should be positioned at base temperature position, close to the resonator and the connected device. Although the focus of the present design is to prove the principle of integrated active impedancemetry, improvements are needed to measure devices at sub-K temperatures with the limited cooling power of typically 500 μW.
Further work towards lower noise and lower power design with more accurate high-frequency models of transistor characteristics at cryogenic temperatures will improve the final performance. Measuring multiplexed out-of-chip capacitances of quantum devices will be also promising for the systematic screening and testing of many quantum devices with a simpler experimental setup than reflectometry. In the long run, the realization of tailored high-end analog electronics at cryogenic temperatures will improve and accelerate the up-scaling of quantum processors.
METHODS
Fabrication details
The impedancemetry chip was designed in a commercial CMOS with the adoption of FD-SOI 28 nm technology with low-Vth thin oxides (GO1) for both the circuit transistors and the DUT nanotransistors. The chip is wire-bonded onto a QFN48 package directly soldered on a 4-layer printed circuit board (PCB) with a FR4-grade fiber-epoxy substrate.
Measurement setup
The PCB was placed at the end of a dip stick enclosed in a metallic container filled with a small amount of helium gas for thermal exchange with a liquid He bath at 4.2 K (see Supplementary Material VI). A PCB-mounted thermometer ensures a precise monitoring of the PCB temperature. High-frequency lines of Vin and Vout were routed on the PCB from the chip package to miniature coaxial connectors via a top-layer 50 Ω-matched coplanar waveguide with ground plane and via fencing. Supply lines were decoupled from environmental noise with PCB-mounted capacitors (0.1, 1, 10 μF) and conveyed to room temperature with copper wiring. All other DC lines were conveyed to ambient temperature with 50 to 130 Ω constantan wiring. At ambient temperature, electronic apparatus is comprised of a multi-channel low-noise 21-bit digital-to-analog converter and a 600 MHz lock-in amplifier.
MISCELLANEA
Supplementary materials Supplementary data to this article can be found online at https://doi.org/10.1016/j.chip.2023.100068.
Acknowledgments This work was partly supported by the European Union's Horizon 2020 Research and Innovation program under Grant Agreement No. 810504 (ERC Synergy project QuCube).
Declaration of Competing Interest The authors declare no competing interests.
