Ring-VCO-based phase-locked loops for clock generation - design considerations and state-of-the-art

Shiheng Yang; Jun Yin; Yueduo Liu; Zihao Zhu; Rongxin Bao; Jiahui Lin; Haoran Li; Qiang Li; Pui-In Mak; Rui P. Martins

doi:10.1016/j.chip.2023.100051

Chip >

2023 , Vol. 2 >Issue 2: 100051 - 10

DOI: https://doi.org/10.1016/j.chip.2023.100051

Review article

Ring-VCO-based phase-locked loops for clock generation - design considerations and state-of-the-art

Shiheng Yang ^,¹^,^* ,
Jun Yin ^,²^,^* ,
Yueduo Liu ¹ ,
Zihao Zhu ¹ ,
Rongxin Bao ¹ ,
Jiahui Lin ¹ ,
Haoran Li ² ,
Qiang Li ¹ ,
Pui-In Mak ^,²^,^* ,
Rui P. Martins ²^,³

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¹ School of Integrated Circuit Science and Engineering, University of Electronic Science and Technology of China (UESTC), Chengdu 610054, China
² State- Key Laboratory of Analog and Mixed-Signal VLSI/Institute of Microelectronics, and the Faculty of Science and Technology, Department of ECE, University of Macau, Macao 999078, China
³ On leave from Instituto Superior Técnico, Uni-versidade de Lisboa, Lisbon 999022, Portugal

E-mails: ysh@uestc.edu.cn (Shiheng Yang),

junyin@um.edu.mo (Jun Yin),

pimak@um.edu.mo (Pui-In Mak)

Received date: 2023-02-14

Accepted date: 2023-04-16

Online published: 2023-04-28

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Abstract

This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator (VCO)-based phase-locked loops (PLLs) for clock generation in different applications. Particularly, the objective of the current work is to evaluate the required PLL performance among the fundamental metrics of power, jitter and area. An in-depth treatment of the mainstream PLL architectures and the associated design techniques enables them to be compared analytically and benchmarked with respect to their figure-of-merit (FoM). The paper also summarizes the key concerns on the selection of different circuit techniques to optimize the clock performance under different scenarios.

Key words： Clock generation; IC design; Phase-locked loop (PLL); Frequency synthesizer

Cite this article

Shiheng Yang , Jun Yin , Yueduo Liu , Zihao Zhu , Rongxin Bao , Jiahui Lin , Haoran Li , Qiang Li , Pui-In Mak , Rui P. Martins . Ring-VCO-based phase-locked loops for clock generation - design considerations and state-of-the-art[J]. Chip, 2023 , 2(2) : 100051 -10 . DOI: 10.1016/j.chip.2023.100051

INTRODUCTION

In modern system-on-chips (SoCs), a reliable clock signal is essential for scheduling the data processing sequences in a wide variety of modules. In modern CMOS technologies, the phase-locked loop (PLL) is the mainstream clock generation circuit. Compared with the inductor-capacitor (LC) voltage-controlled oscillator (VCO)-based PLL, the ring-VCO-based PLL is endowed with a number of compelling benefits: (1) tiny area; (2) free from frequency pulling induced by magnetic coupling; (3) wide frequency tuning range, and (4) multi-phase outputs. Besides, the ring-VCO can be compatible with the digital logic design. Moreover, the ring-VCO tends to exhibit poorer phase-noise performance compared with the LC-VCO, which impedes its exploitation in jitter-demanding applications.

Different functions in an SoC require diverse specifications to their clocks. Each PLL deserves certain customization so as to befit distinct applications, such as digital processors, data converters, wireless and wireline communication interfaces^1,2. For example, in wireless systems, different operation frequencies and modulation schemes are required to support multiple standards^{3⇓⇓⇓⇓⇓⇓⇓⇓⇓⇓⇓-15}, many wireline systems require multi-phase outputs to increase data interaction^16-22 clocks with fast locking time improve the power efficiency in both the memory interfaces and the Internet-of-Things (IoT) devices so as to minimize the energy loss^{11,23⇓⇓⇓⇓⇓-29}, some microprocessors demand a wide frequency range to cover enough operation schemes^30⇓-32. In addition to such dedicated requirements, low jitter, small power and area are the fundamental design goals to improve the competitiveness of the overall SoC solutions. The successive and consistent architecture iterations in the past decades have continuously pushed the overall performance envelope forward.

A low-jitter clock is crucial to underpin high-precision signal processing. For example, for the 5G radios to use the 64-QAM at a 40-GHz carrier frequency, the clock jitter is required to be < 126 fs to withstand an acceptable error vector magnitude (EVM), and the value is reduced to 63 fs for a 256-QAM, which is a very challenging specification and remains a bottleneck for the overall transceiver chain^{12,13,33⇓⇓⇓⇓⇓⇓-40}. For the signal sampling in the analog-to-digital converter (ADC), the signal-to-noise ratio (SNR) is severely affected by the clock jitter. An ultra-low jitter clock is required to avoid the SNR degradation, e.g., a 12-bit 10-GHz ADC can only tolerate a sub-10 fs of jitter. Furthermore, the introduction of faster ADCs requires even lower jitter PLLs to sustain the doubling of receiver baud rate every three years³⁴.

With the rapid development of IoT applications in relevant standards, such as WiFi, Bluetooth Low Energy (BLE) and ZigBee, etc., the clock jitter requirement has a sufficient redundancy, but the power consumption arises as the priority^{23⇓⇓⇓⇓⇓-29}. For example, the minimum requirement for the LO phase noise (PN) at 1 MHz offset would be < −110 dBc/Hz, but its power consumption represents a significant portion (∼30% to 50%) of the total RF transceiver. Consequently, in order to extend the battery life and reduce the labor cost of battery replacement for IoT devices, it is necessary to entail ultra-low power clocks. The situation tends to be worse if the system power-up depends on harvesting the energy from the ambient environment²⁷. Similarly, ultra-low power clocks significantly improve the energy efficiency of the high-speed data links.

Different modules require multiple PLLs to provide different clocks that take a large portion of the area². Compact PLLs are essential^{41⇓⇓⇓⇓⇓⇓-48}, they can not only save the area for other circuits to improve the performance and add functional features, but also save the cost to stay competitive in the market, especially in pricy advanced technology nodes. Furthermore, the chip area determines the final product solution embedded within tiny devices, especially in wearable IoT applications.

In order to fulfill diverse clock requirements, a generic PLL architecture is no longer viable to fit all. In the article, the aim is to overview the related circuit techniques and architectures according to different performances, e.g., the hybrid architecture, the low-jitter and the area-reduction techniques that optimize the key performance metrics such as power, jitter and area. Finally, attempts were made to classify the PLL design techniques with the aim of improving the jitter performance, power and area for various possible applications, so that the readers can easily gain some insights on PLL selection.

LOW-JITTER TECHNIQUES

A large PLL loop BW can better suppresses the VCO's PN, thus exhibiting a low-jitter performance. Yet, f_REF (f_BW < 0.1f_REF) always limits the maximum achievable BW in a conventional type-II PLL due to stability issues. For the LC-type VCO, its high-Q tank with a low PN compensates the small BW. The ring-type VCO exhibits the characteristics of wide frequency tuning range and compact area, while its PN is at least 20 dB higher than its LC counterpart. Fig. 1 illustrates a carrier output frequency of 2 GHz for the ring-type and LC-type VCOs, respectively. To achieve the same PN contribution from the VCO, the BW for the ring-VCO (18 MHz) is 100x larger than that of the LC-type VCO (0.18 MHz). Thus, in order to extend the BW for noise suppression, a conventional type-II design is inappropriate. Consequently, several low-jitter techniques have emerged in recent years to surmount the BW limitation.

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Fig. 1. Illustration of phase noise suppression in different bandwidths for the ring-VCO and LC-VCO. The flicker noise is ignored for simplicity.

ILCM and MDLL

The injection-locked clock multiplier (ILCM) and the multiplying delay-locked-loop (MDLL) have attracted great attention as they can effectively suppress the VCO PN^49-63 and avoid the BW-stability concern of the traditional type-II PLLs. For ILCM, it is possible to achieve a free-running VCO which is injection-locked by the N^th harmonic of the reference clock⁶⁴. However, MDLL is a kind of hard injection in which a clean reference edge is realigned to replace the noisy oscillator edge, thusclearing out the jitter accumulation. On the other hand, a first-order high-pass filter at the BW ∼f_REF/4 equivalently suppresses the PN. It is woth noting that the PN out of band of both ILCM and MDLL is roughly 3 dB higher than that of the same VCO in free running⁶⁵. However, due to their large BW, in-band noise is well suppressed, and the overall noise performance of ILCM and MDLL is greatly improved.

For both ILCM and MDLL, the free-running output frequency (f_OUT) is locked to multiple of f_REF. The narrow locking range is sensitive to PVT variations which cause frequency shift. This effect will result in frequency deviation from the target frequency, leading to a deterministic error in the output. To address this issue, a calibration loop is implemented by tracking the temperature and supply variations continuously in the background^{53⇓⇓⇓⇓⇓-59}. For example, a dual loop of two identical DCOs is implemented⁵⁶. Dual DCOs not only bring matching issues, but also take up ∼30% of the chip area and consume an additional 0.63 mW when the calibration is on. In ref.⁵⁹, the TDC extracts and calibrates the error in the digital domain. With the precision limited by the TDC resolution, a total area of 0.4 mm² and a power of 28.6 mW are dissipated to achieve 130 fs jitter and -64 dBc reference spur. Hence, calibration with low power and small area is preferable to correct the deterministic error. Additional offset and mismatch issues are critically concerned to degrade the performance. Recently, the static offset has been avoided by implementing a delay line to store the timing information, either in the digital domain⁵¹ or analog with enough resolution^60,61. Since the jitter performance degraded rapidly with frequency increases, MDLL with a selective pulse window to replace the edge is more sensitive. While ILCM is more suitable to be implemented for higher frequency generation like 8 GHz⁶².

Type-I PLL

The type-I PLL contains only one integrator from the VCO and therefore there exists only one pole at the origin. Compared with the type-II PLL, its loop stability is more rigorous, and can reach a larger BW. Yet, the conventional type-I PLL employs an RC-based loop filter, thus suffering from a trade-off between the loop BW and REF spur. There exist notches around reference frequency and its harmonics for the transfer function of a master-slave sampling filter (MSSF)⁸, which could suppresses the voltage ripple at the control voltage of the VCO, thus maintaining a low REF spur at a large loop BW. The voltage ripple can be further improved by reducing the duty cycle of the clock control for the MSSF²⁷. The harmonics are attenuated accordingly with respect to the duty cycle. Or using a current reuse technique to isolate the sampling disturbance while maintaining a higher phase detection gain⁶⁶.

Fig. 2 plots another issue of the Type-I PLL, a peaking that appears in the transfer function at a large loop BW due to the degraded phase margin. The peaking magnitude grows with the BW, which offsets the jitter reduction offered by a wide BW. Fig. 3 depicts the simulated RMS jitter as a function of the closed-loop BW for the type-I PLL using an MSSF and assuming that the ring VCO PN is − 90 dBc @1 MHz offset. The noise peaking slows down the jitter reduction with the increase of BW. When the BW exceeds 0.54f_REF, corresponding to a phase margin of 40°, the jitter increases instead. The simulated jitter of the ILCM was also plotted by employing the same ring VCO in Fig. 3, which reveals that the ILCM can achieve a better jitter performance. Here, the RMS jitter reduction of the ILCM also slows down at a large loop BW due to the fact that the locking strength β is changed to alter the loop BW, and the out-band phase noise increases with β, which partially cancels out the jitter reduction⁵².

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Fig. 2. Simulated phase noise profile of the Type-I PLL at different loop bandwidths.

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Fig. 3. Integrated jitter versus loop bandwidth for the Type-I PLL and the IL-ring-VCO.

The noise peaking in the type-I PLL could also be explained in the time domain. Unlike the edge realignment method that clears the jitter by directly tuning the output phase without affecting the VCO frequency, the type-I PLL can only change the output phase by tuning the VCO frequency. If the BW is too wide with the VCO frequency over-corrected, extra phase errors will occur, which could induce the noise peaking in the time domain. The fast phase error correction (FPEC) technique can avoid the noise peaking in Type-I PLL at a large loop BW by making the VCO frequency tunable within a REF cycle⁶⁷. At the beginning of each REF cycle, the proportional path gain of the loop filter enlarges for a short time, resulting in a large frequency jump and rapid clearing of the instantaneous phase error. In the remaining time, the proportional path gain decreases to reduce the VCO frequency jump, which can avoid the frequency over-correction. Overall, the FPEC technique improves the jitter performance of the type-I PLL at a large BW. By avoiding the direct reference injection, the circuit can reach a low reference spur without the need of an auxiliary FLL.

f_REF multiplication One straightforward method to extend the BW is to increase f_REF. Larger f_REF can not only lead to noise suppression of the VCO, but also reduce the in-band noise by lowering the multiplication factor, N. Typically, f_REF with an off-chip crystal oscillator that offers an excellent performance against PVT variations could be obtained, with its frequency usually < 100 MHz. Since the crystal manufacturing process becomes more complex for mass production and the corresponding cost increased significantly, a larger f_REF > 100 MHz is rare.

In order to achieve a large BW with a small f_REF, the implementation of frequency multiplication techniques^{14,49,50,68⇓⇓⇓⇓-73} is required to double^{50,68⇓⇓-71} quadruple^14,49 or octuple⁷² the f_REF. The BW extends along with the f_REF multiplication. With the doubling of f_REF, the PN from the VCO can be reduced by 6 dB. Thus the integral PN for jitter can be reduced by 3 dB.

The f_REF multiplication technique could reduce the VCO noise contribution with the multiplication ratio limited to eightfold. Since the focus of the design moves toward period equalization by duty-cycle correction, it becomes more complex as the multiplication ratio increases. The precise voltage or delay references are in need to minimize the spur level. For the reference doubler, the duty cycle can be background calibrated with delay control⁷¹. For the reference quadrupler⁴⁹, precise voltage references and pure sinusoidal reference waveform are utilized to provide more information. To octuple the reference clock frequency, an RC network is used to generate multiple phases and complex correlation should be carefully background calibrated⁷². Meanwhile, the power consumption also increases from 0.5⁷¹ to 0.76⁴⁹ and 1.8 mW⁷², respectively, with the reference clock frequency doubled, quadrupled and octupled. When compared with solely doubling the VCO power for a 3-dB PN improvement, it is still worth implementing f_REF multiplication techniques with better power efficiency for most cases. To realize an overall design consideration about BW, power and spur, a reference doubler is commonly employed to extend the BW without making much design effort^{50,68⇓⇓⇓-72}. As an individual block, frequency multiplication can be used as an input clock source and cooperate with other techniques for any type of PLLs.

Over-sampling techniques

As mentioned earlier, increasing f_REF can straightforwardly extend the BW thus, the increased f_REF can lead to a more frequent and fast phase detection to calibrate the loop. In other words, if the phase OSR times at each reference cycle within the loop can be detected, the BW can be equivalently extended by OSR times higher than the original, where OSR is the over-sampling ratio and the technique is known as over-sampling^74⇓-76.

Conventionally, the phase error in the time domain can be detected with an operation frequency limited to f_REF. The reference clock, which is generated from a crystal oscillator and followed by a reference buffer, could convert the sinusoidal wave into a square wave. Therefore, although only the timing information at the zero-crossing point is kept, the voltage information is lost.

To obtain over-sampling, the reference clock is directly given by the XO without any modification for phase detection. The original sinusoidal wave preserves the voltage information and it can be fully utilized for over-sampling detection. The waveform-shaping reference buffer can be eliminated to save power, and meanwhile the ultra-low in-band PN is also retained. However, the sampling technique should be carefully applied to the XO for avoiding direct disturbance causing the frequency shift or noise injection. Source-follower buffer can be added to isolate the disturbance and to preserve the sinusoidal wave at the same time.

Intrinsically, a larger over-sampling ratio is preferable for a larger BW. Yet, with the increase of the ratio, a large number of parallel comparators are required^75,76, new design issues are introduced and tend to be more prominent, such as the complicated calibration involving gain variation, power consumption and voltage offset, etc. A compromise should be allowed to optimize the jitter and power performances. In general, either f_REF multiplication or over-sampling technique involve complex calibration. Also, the disturbance and noise injection to the XO should be carefully concerned once the XO is directly sampled.

Sub-sampling PLL

Compared with the conventional type-II PLLs, a very high loop gain can be realized by sub-sampling PLL^35,40,77-79 to suppress the in-band CP noise. In contrast to the classical type-II PLL with 20logN noise amplification of the CP when referred to the PLL output, there is no N² factor for the CP noise in the sub-sampling PLL. It becomes more advantageous with the increase of N, such as for tens of GHz clock generation. The detection gains can be calculated for both the classical PFD-based type-II PLL and the sub-sampling PLL as follows⁷⁹:

(1)

K_{CP, PFD} = \frac{I_{CP}}{2 π} \cdot \frac{1}{N}

(2)

K_{CP, SS} = A_{VCO} \cdot \frac{2 I_{CP}}{V_{GS}}

(3)

\frac{K_{CP, SS}}{K_{CP, PFD}} = N \cdot 4 π \cdot \frac{A_{VCO}}{V_{GS}} ≫ 1

Theoretically, from (3), the enhancement of the detection gain is more than 4πN times (A_VCO/V_GS > 1), much more noise suppression is provided for the CP in the sub-sampling PLL. In addition, the in-band noise contribution from CP is uncorrelated with N. The circuit solely determines its in-band noise contribution by itself. In principle, since it is also a type-II PLL, its bandwidth is limited by the stability issue. Owing to the large loop gain provided by K_CP,SS, a large capacitor and pulse are necessary, followed by the CP to ensure loop stability. Except for the ultra-low-jitter performance provided by the sub-sampling technique, a frequency-locked loop is unavoidable to assist the loop for correct locking operation. Due to the periodical frequency modulation from the front-end and back-end of the VCO, the sampling-induced reference spur is also a problem. Yet, several techniques can alleviate it, such as an additional DLL loop⁷⁸ or indirectly sampling the VCO output to isolate the interference⁴⁰.

Reference-sampling PLL

To circumvent the tradeoff of spur and power performance in the sub-sampling PLL, here the reference-sampling PLL is introduced^{8,70,80⇓⇓⇓-84}. The sinusoidal-wave reference clock can be directly used for sampling^80,81. The circuit avoids the power-hungry reference buffer and the sampling-modulated reference spur, it also extends the capture range of the phase detector from half of the VCO cycle to half of the reference cycle. With a wide capture range of the reference sampling, the additional frequency-locking loop is redundant.

Since the slope of the reference-sampled clock is gentler than that of the VCO output, the phase detection gain is around N times smaller in the reference-sampling PLL. The BW is obviously smaller to have less noise suppression for the VCO. The output noise is totally dominated by the VCO for the whole band, indicating that the BW is not large enough⁸¹. This is not an issue for a low-noise LC VCO, and it still can achieve a jitter power performance of 110 fs and 3.7 mW, resulting in a figure-of-merit (FoM) of − 253.5 dB. Yet, in order to achieve an optimal noise performance with a low-power VCO, it is mandatory to enhance the phase detector gain. With the reference sinusoidal wave reshaped to a square-wave-like signal, the slope can be changed to tune its edge transition time. Furthermore, the detection gains can be calculated for the reference sinusoidal-wave and square-wave sampling as below^53,81,85:

(4)

K_{RF, Sine} = \frac{2 A_{REF}}{N}

(5)

K_{RF, Square} = \frac{T_{REF}}{2 π \cdot τ_{rising}} \frac{A_{REF}}{N}

(6)

\frac{K_{RF, Square}}{K_{RF, Sine}} = \frac{T_{REF}}{4 π \cdot τ_{rising}} ≫ 1

From (6), T_REF and τ_rising denote the reference period and the rising time of the reshaped waveform, respectively. The phase detection gain depends on the edge slope, with its value greatly enhanced without shrinking the locking range, but the locking time may be prolonged. However, the in-band noise of CP remains multiplied by N times compared to the sub-sampling PLLs. Due to the enhanced gain of the square-wave sampling, its noise contribution is negligible. The circuit isolates the sampling modulation spur from sub-sampling. Only the feedforward disturbance remains, such as the reference clock feedthrough and charge injection. The adoption of various techniques can minimize these issues. The core issue of implementing the sampling technique is to enhance the phase detection gain to increase the loop gain and thus the loop BW.

AREA-REDUCTION TECHNIQUE

As shown in Fig. 4, in order to obtain ultra-compact area, most designs are all-digital, fully synthesized or a hybrid. A pure analog design is not adequate for area reduction, which could be mainly ascribed to the use of passive capacitors that occupy a large portion of chip area for loop stability concerns, and the magnitude of the spurious-noise filtering in the control voltage. To minimize the area occupation, large-sized passive components such as resistors, inductors, and capacitors should be avoided. Transistors are preferable for full implementation, e.g., synthesized logic⁴⁷ and the active filter⁴⁸. This superiority tends to be more evident in the advanced process nodes. Yet, certain designs with small capacitors could also exhibit a compact area, like the switched loop filters⁸ or passive integrators⁸⁶. Since the advanced processes inherently take advantage of a smaller area, the area was normalized, which implies that it is not relevant to the process of fairly evaluating the circuit design.

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Fig. 4. Benchmark performance of FoM expressed in (11) and normalized area for the state-of-the-art ring-VCO-based PLLs.

Fully-synthesized PLL

Fully-synthesizable digital PLLs are preferable for consistency and compatibility with the digital system. It can be expressed in a hardware description language and automatically synthesized from a standard-cell library using EDA tools^{46,47,87⇓⇓⇓⇓⇓⇓⇓-95}. The complex layout efforts of analog design are eliminated, and the portability and scalability are significantly enhanced. With the whole circuits implemented at the transistor level without any passive devices, an automatically routed layout with minimum distance pulls off an ultra-compact area, e.g., 0.048 mm^{2 87} and 0.0047 mm^{2 90}. However, compared with the conventional manual-designed PLL, a performance gap still exists. The noise-sensitive blocks, such as the VCO and TDC, cannot be fully optimized due to the unaltered transistor size and layout route. To overcome this issue, some design techniques such as injection-locked PLL, can be implemented to improve the jitter performance. For example, a 0.42-ps jitter at 3.8 mW of power is achieved⁹⁰.

Hybrid integrator

To reduce the PLL area, a ring-VCO is preferable to its LC counterpart. Even though it suffers from a poorer PN, it can be compensated with the BW extension technique. To realize the frequency tuning, compared with the switched-capacitor scheme, a fine resolution was adequately reached with the wide utilization of voltage varactors. To correct its frequency and phase error, the circuit can be equiped with an analog charge pump⁹⁶, a digital-to-analog converter^97,98, time-based integrators^48,99,100 or passive charge-sharing integrator⁸⁶. To cope with the ring VCO and realize area reduction, a proper integrator should be utilized.

In the analog charge pump, the analog mismatch as the reference spur in the output is unavoidably to occur, and an extra circuit technique is needed to compensate for it¹⁰¹. In addition, a large-size capacitor (tens of pico-farads) adopted in the loop filter ensures enough phase margin and tends to be worse as the f_REF drops. The capacitor area, as well as the minimum supply voltage to keep a sufficient voltage headroom, is not friendly along with the downscaling process.

In the conventional current-steering DAC, compact digital circuits replace the area-penalized capacitor in the loop filter, whereas the quantization error remains a problem. In order to reach extremely fine resolution and linearity, a large number of control bits obtained via area-penalized binary to thermometer decoding are required^102,103. Every single bit resolution enhancement requires an exponential increase in the area and power.

The delta-sigma DAC architecture alleviates the design complexity by truncating the multi-bit control with a significant bit reduction to a few bits⁹². But a low-pass filter (R_LPFC_LPF) is necessarily required to suppress the delta-sigma modulator-induced high-frequency quantization error. Such architecture associates the BW corner setting of the low-pass filter with the clock frequency of the sigma-delta modulator. A delta-sigma modulator usually calls for a high-frequency clock to minimize the in-band quantization noise, which is however at the cost of large power consumption or vice versa. The utilization of a small BW set by the RC low-pass filter penalizes the area, which results in a power-area distribution dilemma.

The time-based active integrator utilizing current-controlled ring oscillators is fully implemented with transistors, which greatly reduces the area^48,99,100 and has the potential to operate at a low supply voltage, and is also friendly to the process scaling. The active area is shrunk to 0.0021 mm^{2 48} and 0.0049 mm^{2 98}, however, the overall performance is heavily restricted by the amount of power consumed to operate with a high frequency and its poor PN.

The charge-sharing-based passive integrator utilizes the switched capacitors for the integration. The power consumption of the passive CS-integrator is negligible since the power is mainly originated from the charging/ discharging power with femtofarad capacitance. To set a different capacitor ratio, the voltage resolution can be easily scaled without adding power or design complexity. Unlike the capacitors in the RC low-pass filter that should have a certain small BW with tens of pico-farads, the capacitance in the charge-sharing integrator can be as small as possible to reduce the area, this is mainly ascribed to the fact that the capacitor ratio determines the voltage resolution rather than their absolute values. The capacitors are set as 4 fF and 1.2 pF⁸⁶, respectively, the circuit achieves an ultra-compact area of 600 µm² for the PLL, without deteriorating the output PN.

BANG-BANG PHASE DETECTOR - BBPD

It has been demonstrated that a Bang-Bang Phase Detector (BBPD) can attain the same noise performance at low power and low complexity as the multi-bit TDCs^{10,38,77,102,64,65,104⇓⇓⇓⇓⇓ -110}. Conventionally, to obtain 1-bit more of resolution, the area and power for the multi-bit TDC should be doubled. These ADC-related techniques transfer the voltage to the time domain in a quite complex way; besides this, the finite resolution can distort the data modulation and spectral mask near the integer channels. BBPD is of great power and area efficiency, it relaxes the design of other blocks to improve the performance. But the limited information provided by the 1-bit output severely prolongs the locking time of the BBPD-based PLL.

JITTER AND POWER ANALYSIS

Jitter represents clock precision and is crucial for data processing, and it consists of two components: one deterministic (

σ_{d e t, t}

) and the other random (

σ_{r m s, t}

). The deterministic jitter error induced by the reference spur put forward a more stringent requirement to fulfill the increasing demands of data processing for both wireless and wireline communications. To support the complex modulation and high-speed data rate, efforts made to minimize the impact of the reference spur are essential to improve the performance of the bit error rate. The following expression could be employed to predict the reference spur (dBc)³⁸:

(7)

S p u r = 20 \log_{10} (\frac{N Δ f}{f_{OUT}})

where,

Δ f

is the frequency error between the VCO frequency and desired frequency, and N is the multiplication factor. It can be observed that the requirement of

Δ f / f_{OUT}

is stringent for a larger N, leading to a more challenging frequency calibration.

To evaluate the deterministic jitter, it is necessary to convert the reference spur to the time domain as follows:

(8)

σ_{det, t} = \sqrt{\frac{10^{S p u r / 20}}{2 π \cdot f_{OUT}}}

where, spur and f_OUT denote the reference spur and the output frequency, respectively.

σ_{total, t}

represents the total jitter as:

(9)

σ_{Total, t}^{2} = σ_{det, t}^{2} + σ_{rms, t}^{2}

Fig. 5 illustrates the spur impact on the total jitter, assuming the PLL operates at 2.4 GHz. If the total jitter is 2 ps and the noise contribution by

σ_{det, t}

drops from 20% to 1%, it leads to a spur reduction of 26 dBc. Similarly, if the ratio of

σ_{det, t}

σ_{Total, t}

remains constant by 1%,

σ_{Total, t}

is improved from 2 ps to 100 fs, requesting a spur reduction from −73 to −99 dBc. The spur requirement is relaxed for large

σ_{Total, t}

and increases dramatically as

σ_{total, t}

becomes lower.

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Fig. 5. Illustration of the spur impact on the total jitter performance.

Two alternatives could be employed to improve the jitter performance: lower the PN of the VCO or enlarge the loop BW. The ring-VCO architecture is simple. Its PN is proportional to the power budget, with an almost constant FoM. For example, from Fig. 6a, a first-order high-pass filter with a BW of 5 MHz suppresses the VCO PN. In order to achieve a jitter < 300 fs, the VCO's power budget is ∼4 mW. For a more stringent jitter requirement, e.g. < 180 fs, the VCO's power budget should be ∼10 mW. In fact, the performance may saturate, then it is more likely to design the VCO with limited power and PN, with the power fixed to 6 mW and the PN as −105 dBc @1MHz offset frequency. To obtain the same jitter performance of < 200 and < 100 fs, a loop BW of 7 and 20 MHz is required, respectively, as illustrated in Fig. 6b. Hence, to achieve an ultra-low jitter clock, either larger power consumption for the ring-VCO with a decent PN, or a larger loop BW for more noise suppression is necessary.

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Fig. 6. a, Illustration of VCO power and jitter correlation at a loop BW of 5 MHz. b, Illustration of jitter and BW correlation at a VCO power of 6 mW.

A simple power distribution of the PLL consists mainly of the power dissipated on the loop (P_Loop) and the VCO (sub):

(10)

P_{Total} = P_{Loop} + P_{VCO}

Ideally, the most efficient approach for the design is to nullify P_Loop (

P_{Loop} \approx 0

) and consume the power mainly on the VCO (

P_{VCO} \approx P_{Total}

). The noise contribution from the loop is also assumed to be negligible. As such, the power cost on the VCO can be fully utilized to enhance its noise improvement. Some differential delay cells^111,112 are capable of achieving better PSRR and relieving the requirements of LDO, while their phase noise is poorer than that of the single-ended ones. Even though differential type exhibits better noise immunity than the single-ended, it is still far from enough. LDOs and some substrate isolation are always implemented to suppress the environmental noise for practical use¹¹³. For example, there are two cases with the same FoM but different power distributions: Case A:

P_{Loop} = 0.3 mW

and

P_{VCO} = 1 mW

, and Case B:

P_{Loop} = 2 mW

and

P_{VCO} = 3 mW

. Case A can exhibit a better power efficiency, but it is more challenging for the loop design at such a low power budget to prevent in-band noise degradation. To approach a higher FoM, it is necessary to increase the ratio of P_VCO/P_Total; one way is to enlarge P_VCO to achieve low noise and another way is to lower P_Total by minimizing P_Loop. Apparently, increasing P_VCO is easier than reducing P_Loop to improve FoM. Thus, a design with the same FoM but smaller P_VCO and P_Loop is preferable for low-power applications. Similarly, for a design to reach its best peak FoM, it is only necessary to replace P_Total with P_VCO:

(11)

Fo M_{Ideal} = 10 \log_{10} [\frac{σ_{total}^{2}}{1 sec} \cdot \frac{P_{VCO}}{1 mW}]

Fo M_{Ideal}

can also be adopted to evaluate the performance limit of different types of circuit architectures. Also, the difference between FoM and FoM_Ideal can represent the loop efficiency:

(12)

Δ FoM = FoM - Fo M_{Ideal}

From Fig. 7, good power efficiencies and ultra-compact areas could be achieved by the designs with switched-loop filter and passive charge-sharing integrator. Whereas, the active integrators and complex loop calibrations are not beneficial for improving the power efficiency. Furthermore, digital implementation in a loop shows advantages over others in reaching lower spur and power as opposed in Fig. 8.

View original graphic|Download|PPT slide

Fig. 7. Benchmark performance of ΔFoM and area for the state-of-the-art ring-VCO-based PLLs.

View original graphic|Download|PPT slide

Fig. 8. Benchmark performance of ΔFoM and spur for the state-of-the-art ring-VCO-based PLLs.

Similarly, most of the ring-VCO-based PLLs with better FoMs exhibit a limited N, which is typically < 40⁷². This imposes restrictions on practical implementation, e.g., low-cost crystal oscillators providing a reference frequency of normally < 100 MHz. It is of difficulty and high expenses to obtain a higher reference frequency in terms of fabrication. Consequently, N becomes the limiting factor for generating a higher output frequency. Also, for ILCM and MDLL, their operational stability, jitter performance and timing margin degrade rapidly with the increase of N⁶². N is not included in the original FoM¹¹⁰ and the impact couldn't be differentiated due to the weak correlation between FoM and N, and the FoM goes up as f_REF increases. In this case, FoM_R will be more suitable to benchmark the ring-VCO-based PLLs with f_REF and f_OUT. However, it tends to be more challenging to achieve the same FoM and design with a lower reference frequency or a higher output frequency.

Likewise, the FoM can be further derived as FoM_R⁹⁷ and FoM_N^49,67,71,72, respectively:

(13)

Fo M_{R} = 10 \log_{10} [\frac{σ_{Total}^{2}}{1 sec} \cdot \frac{P_{Total}}{1 mW} \cdot \frac{f_{REF}}{1 MHz}]

(14)

Fo M_{N} = 10 \log_{10} [\frac{σ_{Total}^{2}}{1 sec} \cdot \frac{P_{Total}}{1 mW} \cdot \frac{1}{N}]

From Fig. 9, it tends to be more convenient for conducting the designs based on type-I topology and reference multiplication with ILCM/MDLL and oversampling loop at small f_REF and large N.

View original graphic|Download|PPT slide

Fig. 9. Benchmark performance of FoMr, N and f_REF for the state-of-the-art ring-VCO-based PLLs.

FoM DERIVATION

In order to fairly evaluate and compare the performance of the ring-VCO-based PLL, a new FoM which normalizes the parameters of jitter, spur, power, reference frequency, divider ratio and area (normalized to CMOS Tech.) was proposed and defined as follows:

(15)

FoM = 10 \log_{10} [\frac{σ_{Total}^{2}}{1 sec} \cdot \frac{P_{Total}}{1 mW} \cdot \frac{f_{REF}}{1 MHz} \cdot \frac{1}{N} \cdot \frac{Area}{1 m m^{2}} \cdot {(\frac{1 nm}{CMOS Tech .})}^{2}]

For the ring VCO, its PN is mostly determined by the power consumption and slightly affected by the process, so for the sake of simplicity, only the influence of power on the PN performance can be taken into consideration. Since the integrated range of the phase noise usually exhibits an upper limit of 100-MHz offset, it does not include the reference spur power if a reference clock frequency is in the hundreds of MHz. The implementation of a large BW always induces a large reference spur. For example, the BW is inversely proportional to its spur level for the type-I PLL. Thus, the jitter including the spur is much more appreciated. Conventionally, the f_REF directly determines the BW, for example the BW of type-II PLL is usually 10x smaller than f_REF (f_BW < 0.1f_REF), and the BW of ILCM or MDLL is ∼f_REF/4. A larger f_REF leads to a greater noise suppression andlow jitter, and thus a normalized reference frequency is preferable, compared with different f_REF. Similarly, for the same f_REF, different output frequencies which are attained with different flicker noise corners, together with jitter performance, degrade rapidly as N increases, such as ILCM and MDLL, especially for a higher f_OUT. So a larger N is faced with more design challenges. Finally, technology downscaling allows for a smaller chip area, and it is irrelevant to the PLL architecture itself. Thus, a normalized area can distinguish the size of different technology nodes. As a result, the proposed FoM can be used to comprehensively compare and evaluate the performance of the ring-VCO-based PLL with different design perspectives and various design parameters. As a result, their different impacts can be minimized andfull coverage could be achieved. For instance, a large loop bandwidth for suppressing the poor ring VCO noise is mandatory to achieve low jitter performance. In addition, the use of a single external crystal with a smaller frequency to provide the reference clock is also popular in terms of cost and area saving, which requires on-chip reference multiplication or over-sampled phase detection. Last but not least, hybrid implementation is desired to take advantage of both digital and analog circuits. Data processing is more convenient in the digital domain, and precision is also preserved in the analog domain.

CONCLUSIONS

This article detailed different PLL architectures and design techniques based on the performance benchmarks for clock generations. The pros and cons of each PLL architecture and technique were analyzed in detail. In ultra-scaled CMOS technologies and emerging applications, the PLL design is differentiated from the initial classical type-II analog PLL to the various digital-intensive and hybrid architectures. The implementation of other advanced circuit techniques by wisely balancing the power, jitter and area budgets could also achieve a dedicated clock performance. A new FoM was also proposed to comprehensively evaluate the performance of ring-VCO-based PLLs.

MISCELLANEA

Funding This work was partially supported by the National Natural Science Foundation of China under Grant 62004028, 62090041 and the Science Foun- dation of Sichuan under Grant 2022NSFSC0927.

Declaration of Competing Interest The authors declare no competing interests.

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模态框（Modal）标题

Abstract

Cite this article

INTRODUCTION

LOW-JITTER TECHNIQUES

Fig. 1. Illustration of phase noise suppression in different bandwidths for the ring-VCO and LC-VCO. The flicker noise is ignored for simplicity.

ILCM and MDLL

Type-I PLL

Fig. 2. Simulated phase noise profile of the Type-I PLL at different loop bandwidths.

Fig. 3. Integrated jitter versus loop bandwidth for the Type-I PLL and the IL-ring-VCO.

Over-sampling techniques

Sub-sampling PLL

Reference-sampling PLL

AREA-REDUCTION TECHNIQUE

Fig. 4. Benchmark performance of FoM expressed in (11) and normalized area for the state-of-the-art ring-VCO-based PLLs.

Fully-synthesized PLL

Hybrid integrator

BANG-BANG PHASE DETECTOR - BBPD

JITTER AND POWER ANALYSIS

Fig. 5. Illustration of the spur impact on the total jitter performance.

Fig. 6. a, Illustration of VCO power and jitter correlation at a loop BW of 5 MHz. b, Illustration of jitter and BW correlation at a VCO power of 6 mW.

Fig. 7. Benchmark performance of ΔFoM and area for the state-of-the-art ring-VCO-based PLLs.

Fig. 8. Benchmark performance of ΔFoM and spur for the state-of-the-art ring-VCO-based PLLs.

Fig. 9. Benchmark performance of FoMr, N and fREF for the state-of-the-art ring-VCO-based PLLs.

FoM DERIVATION

CONCLUSIONS

MISCELLANEA

References

Links

Fig. 9. Benchmark performance of FoMr, N and f_REF for the state-of-the-art ring-VCO-based PLLs.