Research article

Implementing hardware primitives based on memristive spatiotemporal variability into cryptography applications

  • Bo Liu , 1, * ,
  • Yudi Zhao 2 ,
  • YinFeng Chang 3 ,
  • Han Hsiang Tai 4 ,
  • Hanyuan Liang 5 ,
  • Tsung-Cheng Chen 4 ,
  • Shiwei Feng 1 ,
  • Tuo-Hung Hou 6 ,
  • Chao-Sung Lai , 3, 4, 7, 8, *
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  • 1 Faculty of Information Technology, College of Microelectronics, Beijing Univer- sity of Technology, Beijing 100124, Beijing, China
  • 2 School of Information and Communication Engineering, Beijing Information Science & Technology Univer- sity, Beijing 100101, Beijing, China
  • 3 Artificial Intelligence and Green Technol- ogy Research Center, Chang Gung University, Guishan Dist., Taoyuan 33302, Taiwan, China
  • 4 Department of Electronic Engineering, Chang Gung University, Guishan Dist., Taoyuan 33302, Taiwan, China
  • 5 School of Electrical Engineer- ing and Computer Science, The Pennsylvania State University, University Park, PA 16802, USA
  • 6 Institute of Electronics, National Yang Ming Chiao Tung Uni-versity, Hsinchu 300, Taiwan, China
  • 7 Department of Nephrology, Chang Gung Memorial Hospital, Guishan Dist., Linkou 33305, Taiwan, China
  • 8 Department of Materials Engineering, Ming Chi University of Technology, Taishan Dist., New Taipei City 24301, Taiwan, China
*E-mails: (Bo Liu),
(Chao-Sung Lai)

Received date: 2022-11-16

  Accepted date: 2023-02-17

  Online published: 2024-08-31

Abstract

Implementing hardware primitives into cryptosystem has become a new trend in electronic community. Memristor, with intrinsic stochastic characteristics including the switching voltages, times and energies, as well as the fluctuations of the resistance state over time, could be a naturally good entropy source for cryptographic key generation. In this study, based on kinetic Monte Carlo Simulation, multiple Artificial Intelligence techniques, as well as kernel density map and time constant analysis, memristive spatiotemporal variability within graphene based conductive bridging RAM (CBRAM) have been synergistically analyzed to verify the inherent randomness of the memristive stochasticity. Moreover, the random number based on hardware primitives passed the Hamming Distance calculation with high randomness and uniqueness, and has been integrated into a Rivest-Shamir-Adleman (RSA) cryptosystem. The security of the holistic cryptosystem relies both the modular arithmetic algorithm and the intrinsic randomness of the hardware primitive (to be more reliable, the random number could be as large as possible, better larger than 2048 bits as NIST suggested). The spatiotemporal-variability-based random number is highly random, physically unpredictable and machine-learning-attack resilient, improving the robustness of the entire cryptosystem.

Cite this article

Bo Liu , Yudi Zhao , YinFeng Chang , Han Hsiang Tai , Hanyuan Liang , Tsung-Cheng Chen , Shiwei Feng , Tuo-Hung Hou , Chao-Sung Lai . Implementing hardware primitives based on memristive spatiotemporal variability into cryptography applications[J]. Chip, 2023 , 2(1) : 100040 -12 . DOI: 10.1016/j.chip.2023.100040

Introduction

Throughout the history of mankind, from the ancient Egyptian and ancient Spartan scytale to the Caesar cypher and the Enigma machine in World War II, the development of cryptography guarantees the security of information storage and transmission. Those kinds of cryptography belong to symmetric-key cryptography, which utilizes the same cryptographic keys for encryption and decryption. The weakness of those strategies is that once the key tables are exposed, the cipher failed immediately. Apart from the symmetric-key cryptography, an innovation of asymmetric cryptography was proposed in the 1970s. Rivest-Shamir-Adleman (RSA) is one of the famous and successful examples of the asymmetric cryptography, which is widely used in information security1. The security of the RSA cryptosystem relies on the difficulty of taking discrete logarithms for finding large prime factors of a given product. Although the RSA algorithm provides significant asymmetry between the intended and unintended uses of encoded information, the random number-based key generation for this algorithm is still potentially vulnerable (e.g., the forward secrecy issue). Threatened by the multifarious brute-force attack, cyber-attack, or Trojan implantation from unauthenticated parties, the random numbers in the security system should be intrinsically difficult to replace and predict2-4. Thus, the random number taken in the cryptosystem should be truly random or chaotic in nature. From the above considerations, implementing the physical or hardware primitives into cryptosystem could be a new attempt to enhance the robustness and complexity to guarantee the information security in the current big data era5-8.
Memristor, a key component towards in-memory logic and neuromorphic computing, has realized versatile functions based on its cross-pointed structure9. However, for practical applications, the memristor's intrinsic stochasticity on its switching voltages, times and energies, as well as the fluctuations of the resistance state over time should be carefully considered10. Although many efforts have been made to control the CF location and growth, e.g. nanocone shape Ag electrode11 or graphene as insertion layer for blocking excessive atoms/ions injection into the dielectric,12-16 the intrinsic memristive stochasticity is in turn a naturally valueble entropy source for cryptographic research and applications17-22. In the past few years, especially very recently, the use of the intrinsic memristive variability has aroused world-wide scientific attention in true random number generator (TRNG) as well as cryptographic key generation. In 2015, Balatti et al. constructed a TRNG using the statistical variability of the Set voltage in an oxide-based resistive switching23. In 2016, Wei et al. at Panasonic developed TRNG based on memristive current fluctuation24. In 2017, Jiang et al. utilized the volatile switching in a Ag:SiO2 diffusive memristor to generate high-speed random bits25. Following the work of the Jiang group, Woo et al. constructed a TRNG based on Pt/HfO2/TiN memristor in 201826 and implemented a nonlinear-feedback shift register into the same system in 202027. In 2021, the same Woo group reported high-speed TRNG based on CuxTe1-x diffusive memristor28. And in the same year, Kim et al. proposed a NbOx Mott memristor-based TRNG based on its intrinsic stochastic oscillation29. In 2021, Wen et al. realized advanced data encryption using h-BN based memristor based on its intrinsic random telegraph noise (RTN)30. In 2022, Liu et al. demonstrated the bi-modes entropy sources in a Bi2O2Se-based memristive TRNG, including statistical variability of Set voltages and current fluctuation over time31. Although many successful TRNGs based on the intrinsic memristive stochasticity have been reported, comprehensive studies of the intrinsic memristive stochasticity are still yet to be carried out.
In this study, the memristive spatiotemporal variability within graphene CBRAM has been synergistically investigated based on kinetic Monte Carlo (KMC) simulation, multiple Artificial Intelligence techniques, kernel density map and time constant analysis, which verified the inherent randomness of the memristive stochasticity. The random numbers based on hardware primitives are also passed through the Hamming distance calculation to verify their randomness, uniqueness and reproducibility. For the device architecture, graphene-based conductive bridging RAM (CBRAM) was chosen in the current study due to the dimensional anisotropic characteristics of graphene electrodes: high electrical and thermal conductivity in the plane direction, and low electrical and thermal conductivity in the vertical direction32. This characteristics could facilitate the transportation between device and peripheral circuit as well as inhibit the power consumption during the resistive switching. To analyze the spatiotemporal variability, three types of artificial intelligence (AI) technologies were employed including principal component analysis, long short-term memory and Shapley value. Comparing with the previously reported in-situ material detection or statical calculation, the strategy employed in the current study based on AI technologies provides the D2D correlation and classification analysis and the C2C correlation in long time series. Moreover, integrating the random numbers based on memristive variation into a Rivest-Shamir-Adleman (RSA) cryptosystem has been demonstrated in detail.

Results & discussion

Unlike the metal-oxide-semiconductor field-effect transistors (MOSFET), whose working mechanism relies on a large number of electrons and holes, memristor, in contrast, realizes its resistive switching and information storage only via a limited number of ions within the switching medium33. Fabrication inhomogeneity (e.g. the poly-grain nature of the graphene electrodes, the polymer-assisted transfer/lithography processes, and the subsequently nonuniformity deposition), and the initial formation of conduction filaments as well as its intrinsic stochastic switching mechanism, lead to the memristive device-to-device variability (DDV). Note that the device structure in the current study can be seen in the Fig. 1a and the fabrication details can be found in the Experiments section and Fig. S2 in the Supplementary Materials. A typical resistive switching curve of graphene-based CBRAM have been shown in Fig. 1b. For the Set process, the active electrode (silver in this study) gets oxidized into Ag+ and dissolved into the electrolyte, which is then reduced at the inert electrode surface and piled up as a metallic filament to bridge the active electrode during the Set bias voltage, during which the device is switched to the low resistance state (LRS). When an opposite polarity Reset voltage is applied, the conductive filament starts to be ruptured and the device is switched back to the high resistance state (HRS), which is the Reset process. Considering the differences of fabrications, initial filament formation and variation of repeated cycles and current fluctuation over time, the filament revolution (from Ag to Ag+ and from Ag+ to Ag) can be in highly stochastic, as shows in Fig. 1c. Since the silver cations transport more easily in a defect-rich region with lowest electrochemical potentials, the variability of the CF shape will be formed due to the inhomogeneous nature of the AlOx34. Briefly, the AlOx amorphous electrolyte plays at least 3 roles for the variability during forming process and subsequent multiple cycles35-37: 1. noise source for current fluctuation: the electrolyte may include redox reactions of the Ag atoms or ions at the filament surface, or resulting atomic reversible rearrangements at the metastable positions or the defects sites, which may cause current fluctuation over time; 2. solubility: the CF and sub-filaments (if existed) will be dissolved at various degrees during the gradual Reset operation, which determined the HRS in the following cycle; 3. thermal conductivity: during repeated bias sweeping back and forth, a large amount of Joule heat is generated and accumulated within the electrolyte; Ag nanoparticles will merge into larger clusters to minimize the interfacial energy. As a result, not only the shape of the CF, but also the device performance will be influenced, because both the drift and diffusion current of the Set and Reset processes are thermally accelerated; in other words, whether the heat can be promptly dissipated with the electrolyte is also a stochastic factor to the device switching characterizations. Moreover, considering the weak thermal conductivity of the van der Waals interface of graphene electrode, the memristive variation will be further complicated. To analysis the CCV statistically, conventionally, a large number of IV curves could be analysis via Weibull distribution, time series analysis (TSA) or multivariate strategy to forecast the Set and Reset jointly38. However, they neglect the physical correlation between the cycles. To consider the correlation between cycles, an iterative recurrent neural network based Long Short-Term Memory (LSTM) has been utilized to analyse the CCV of oxide-based memristor successfully. In this work, we extracted the physical parameters from memristive measurements and utilized principal component analysis (PCA) to analyse the DDV and LSTM to analyse the CCV. Moreover, the TTV is also analysed based on physical models, where the TTV under different voltage biases are shown in Fig. 1d1-d3. The device array and the device architecture have been shown in Fig. 1e-g via scanning electron microscope (SEM) observation. To inspect the device vertical structure and the thickness of the electrolyte layer, the transmission electron microscopy (TEM) image is shown in Fig. 1f. Moreover, elemental distribution of the TEM image with energy dispersive X-ray spectroscopy (EDX) including Ag, Al, C, O and Si has been exhibited in Fig. S3a-g in Supplementary Materials. Raman spectrum detecting has been also carried out to verify the high crystallinity and low defect density of the graphene electrode, as shown in Fig. S3h in Supplementary Materials.
Fig. 1. Spatiotemporal variability of memristor. a, The illustration of DDV and the device structure. b, The typical resistive switching IV curves of memristor, where the CC is set as 100 µA to prevent hard breakdown and overshooting, more results of CCV could be found in Fig. 3. c, Energy diagram showing charge transfer of the redox reaction between Ag atom in the filaments and Ag ion dissolved in the AlOx layer; those effects differ from device to device and cycle to cycle, indicating spatiotemporal variability. d, The T2T variability includes the RTN signals, d1-d3 exhibit the current fluctuation under different VBG, ranging from 0 V to -0.2 V, the SEM image of memristor device array (e) and the single device (f). g, The vertical structure of the memristor by TEM observation, where the thickness of AlOx is approximately 6 nm.
To provide more physical understanding and better visualisation of the DDV and CCV during the device operations, a kinetic Monte Carlo (KMC) Simulation is carried out, and described in this section39,40 (more calculation details could be found in Experiment section)41. As shown in Fig. 2a, a series of physical processes are considered in the simulation including anode oxidation (p1), cation hopping within the electrolyte (p2), cation reduction and deposition on cathode (p3), electron emission (p4), electron hopping within electrolyte (p5), electron adsorption (p6), cation and electron reduction (p7). The Fig. 2b illustrate the migration energy barrier of cation and electron, where γ and δ are factors of barrier lowing and a is the effective hopping distance of particles42. For reduction process, kq2/a is the barrier lowing effect due to Coulombic attraction. As shown in Fig. 2c, the Forming process of 4 devices are under same operation and the same physical structure, the filament morphology is distinct from each other (4 more Forming simulation results can be found in Supplementary Materials, Fig. S1a). The Forming process determined the initial conductive filament distribution and locations, as well as the distinct DDV. Considering the poly-crystal nature of graphene and the inevitable polymer residues during the transferring process, the discrepancy of graphene lattice and surface could also improve the complexity the DDV. After the Forming process, a sequential resistive switching has been carried out, as shown in Fig. 2d. Obviously, around the location of the initial filament, there is a higher possibility to form new filaments. Subsequently, during cycle-to-cycle Set and Reset, the filament forms and ruptures in different locations and morphologies. Extended with the Fig. 2d, 8 more simulation results could be found in Supplementary Materials, Fig. S1b. The simulation results are consistent with the recent report on in situ observation of a planar Pt/PEO-Li+/Ag memristor devices43. Based on the direct observation of the CF growth revolution under different devices and repeated cycles, it is evident that the shape, formation position as well as the sub-filaments are in highly variable. The amorphous nature of the electrolyte will result in device to device variation in switching performances. And the preferential formation of CF does not prevent reformation of filaments in new locations, which reveals a high variability from cycle to cycle. As an alternative to the time-consuming in-situ characterization techniques, KMC simulation could provide more results based on the physical understandings and software calculations44. However, moving towards the application of cryptographic key generation, further study to prove that the memristive variation is really random is necessary.
Fig. 2. Kinetic Monte Carlo simulation of graphene CBRAM for visualising DDV and CCV. a, Schematics of the device structure and the holistic filament revolution; including p1: anode oxidation, p2: cation hopping, p3: cation reduction and deposition on cathode, p4: electron emission, p5: electron hopping, p6: electron adsorption, p7 cation and electron reduction. b, Electric field alter the migration barrier of cation and electron; and the reduction of the cation and electron. c, Filament morphology of four different devices after forming process. d, Filament morphology of 4 cycles of Set and Reset, including the first forming process.
Traditional analysis tool presumes the independency between the physical parameters. Moreover, only few parameters, such as Set and Reset voltages are concerned. But based on the physical understanding of the memristor, the CCV is connected from cycle to cycle, e.g., the tunnelling gap formed in the previous filament rupture will affect the new filament formation. In turn, the shape, size, component and element gradients in the new formed filament will also influence the filament rupture in the subsequently cycles45. Scaling to a broader spatiotemporal range, the DDV not only includes the fabrication differences but also the initial formation of the conduction filaments, as well as CCV. TTV is also based on the resistance state, which is also affected by CCV (in other words, the CCV determined the TTV). Thus, utilizing the spatiotemporal variability as hardware primitive, a critical question is that, are DDV and CCV independent of each other or are they physically correlated? Once the attacker obtains their physical correlations, the cryptosystem based on the memristive primitives could be easily encoded.
Although the KMC visualised the DDV and CCV results based on simulation, it cannot tell whether those results are correlated or not. To further analyse the DDV and CCV, artificial-intelligence-based techniques could be a promising strategy46. Eight physical parameters have been extracted from IV curves including the Set and Reset operations (Set Voltage, Current before Set, Reset Voltage and Current, Current and Voltage after Reset) as well as the high resistance state (HRS) and low resistance state (LRS). The HRS and LRS are extracted at the voltage of ± 0.1 V, where the 0.1 V is for the HRS and the -0.1 V is for the LRS. The current and voltage of Set and Reset are extracted from the points after Set and Reset behaviours. The current and voltage after Set and Reset are extracted from the points after Set and Reset. Note that the Set processes are instantaneous, which is easy for extraction. And the Reset processes are gradual, where the lowest current is defined as the switching point for data collection. Before being fed into the following machine learning techniques, all current parameters were subjected to logarithm calculation for feature scaling. To analyse the DDV, we utilized Principal Component Analysis (PCA) to deduce whether the physical parameters from the identical device could be classified into an identical group47. The PCA is to project a high-dimensional node into a low-dimensional space, and the low-dimensional space retains most of the properties of the high-dimensional space. By transforming a sample with n feature spaces into a sample with k feature spaces, where k must be less than n. Such transformation only allows linear transformations. In machine learning, PCA is a frequently used method of feature extraction for dimension reduction, of which the purpose is to reduce the number of dimensions of input data to improve the learning performance, but the overall prediction performance will not be degraded and even become better. 8 devices, each with 5 successive cycles have been taken into calculation. As shown in Fig. 3a, no clear classification can be obtained, which could be a solid evidence for the independency between DDV.
Fig. 3. Artificial intelligence-based analysis of DDV and CCV. a, Principal Component Analysis of DDV. b1, Schematic illustration of long short-term memory cell of cycle i and cycle i+1, where the physical parameter of cycle i (i ranges from 1 to 255) is extracted from IV curves like b2, including HRS current, current before Set, Set voltage, LRS current, Reset voltage/current and current/voltage after Reset. c-j, The distribution of the Set voltage, voltage after Reset, LRS current, current after Reset, Reset current, HRS current, current before Set, and Reset voltage for 256 cycles, where the grey dots indicate voltage values and the blue dots indicate current values. k-l. The SHAP value and the mean value of the SHAP of the contribution of all the physical parameters to the Set voltages.
After the DDV analysis, CCV has been analysed with LSTM technique. The LSTM cell is shown in Fig. 3b. Based on its input gate, forget gate, activation gate, and output gate, the LSTM cell can update the cell state, remove ignorable information and propagate useful information to the next cell via feedback optimization and iterative calculation48. LSTM is a type of recurrent neural network that allows the outputs at a previous time step (physical parameters in the previous cycle in the memristive calculation) to be conjunctively used as co-inputs at the following time step49. Thus, the cycle-to-cycle correlation can be considered in the pointwise multiplication. In this scenario, to predict the Set voltage in a cycle (whether larger or smaller than the threshold voltage), such a recurrent neural network can process not only single data points (the rest of 7 physical parameters), but also entire sequences of 256 cycles. The feature extraction method is shown in Fig. 3b2 and the extracted physical features of those 256 cycles have been shown in Fig. 3c-j. Those extracted physical features are in highly random distribution, which is consistent with the KMC simulation results. To visualise the contribution of those physical parameters to the Set voltages, Shapley value plots were carried out to exhibit the correlation and contribution of CCV. The Shapley value plot is originated from game theory and local explanations, which could concisely leverage and visualise all the features’ contributions into the model's prediction. As shown in Fig. 3k-l, the “Reset Current” and “voltage after Reset” are located at the highest value of the latitude variables, indicating their biggest contribution to the prediction of the Set voltages. There two features are related to the start and the end of the Reset transition process. Although the “Set voltages” belong to the Set process, the physical features in the Reset process provide much bigger contribution and variation, which is due to its higher randomness in nature. Considering the heat accumulation effects, both the drift and diffusion processes will be influenced50. Thus, the gradual Reset process is more complex in nature and also contributes the highest impact on the Set voltages. The “current after Reset” is also an important feature of Reset, but with a much lower contribution to the Set. This result could be attributed to its lower variability compared with the voltage. In other words, the variation of the current amplitude is more dominant during the Reset process. Subsequently, the HRS and LRS also play important roles in “Set voltages”. The HRS is related to the filament gap formed during the previous rupture and the LRS is related to the size, shape, conductivity, and ion gradient of the current filament. These calculation results are different from our recent study, a LSTM analysis of the CCV in a Bi2O2Se-based memristor, which may be due to the different switching nature between redox-based and conductive-bridge-based memristors31,40. The SHAP values exhibiting not only the contribution but also the correlation between input value to the output are visualised. The red dots and blue dots located at the right x-coordinate line indicated a positive/negative contribution to the output value (the Set voltage), and vice versa. As shown in the Fig. 3 a, the red and the blue dots are synergistically overlapped for all the parameters. This result elucidated the inherent stochasticity of the CCV (because the 7 physical features synergistically influence the Set voltage, which is hard to be predicted physically), machine learning attack resilient and physically unpredictable features as hardware entropy source for the random crypto key generation51. The PCA techniques could visualise the classification of physical parameters of DDV and the LSTM with SHAP techniques could analyse in-depth the CCV within single device. Combining these AI techniques could clarify the source of the electrical variation, both for DDV or CCV, which could be a general analysis solution for other device platforms.
Based on the machine learning analysis, the DDV and CCV could be served as entropy sources for cryptography key generation. The random telegraph noise (RTN) is a stochastic current fluctuation between two resistance states. A 0.1 V constant voltage stress (CVS) in 100 Hz with different back gate voltage including 0 V, -0.1 V and -0.2 V, was applied on the graphene based memristor on its HRS state, due to its higher fluctuation than the LRS. Fig. 4a shows the power spectral density (PSD) of three kinds of RTN (0 VBG, -0.1 VBG and -0.2 VBG), evidencing a 1/f behaviour. In a recent study of the RTN based on scanning tunnelling microscope point contact devices, the atomic fluctuation is verified as the dominant noise source52. The noise solely originated from dynamical defects, where atoms are fluctuating between metastable positions and driven by temperature-activated Langevin dynamics53. MATLAB script was carried out to derive the flipping time of the three kinds of RTN signals. Most of the rising and falling transition time located at the region of 0.01 s symmetrically, indicating the same flipping time of rising and falling, as shown in Fig. 4b1 and b2. The time lag plot (TLP) of the three kinds of RTN signals in Fig. 4c-e, shows the distinctive two resistance states, where the left bottom corner is the lower resistance state δ0 and the top right corner is the higher resistance state δ1. Note that there is no transition state in the current study (no points located in the right bottom and top left corners)54. Based on the symmetry distribution of the two states and equal transition time between the two states, the RTN signals provide equal probability for upper and lower current levels. In this scenario, the RTN signals (as shown in Fig. 4f1) could be utilized into random number generation via a binarized algorithm as shown in Fig. 4f2. The Fig. 4h-j exhibited the random number generation from the three kinds of RTN signals. Fig. 4g shows the D flip-flop and comparator-based peripheral circuit to extract and store the RTN signals into the binarized type. More RTN results under 20 Hz, 10 Hz and 5 Hz with 0 V, -0.1 V and -0.2 V back gate voltages have been shown in Fig. S4a-i. The lower frequency-based measurements do not exhibit adequate random bi-state bits, which may be due to their lower detecting rate comparing with the flipping rate of the RTN.55
Fig. 4. RTN analysis. a, Power spectral density. b1-b2, Capture and emission time and, c-e, the time lag plot of the three kinds of RTN signals, where the three kinds of RTN signals are under the VBG 0 V, -0.1 V and -0.2 V, respectively. f1, Demonstration of the RTN signal and f2, the binarized strategy. g, Peripheral circuit of the memristor to extract the RTN signals or the set statics as entropy source (by using different load resistance or comparing voltages). h-j, Exhibitions of the binarized matrix of the binarized random numbers originated from the three kinds of RTN signals.
To generate cryptographic key, the intrinsic stochasticity of the DDV, CCV and TTV have been analysed on the physical level. Before harnessing those hardware-based primitives into the cryptography algorithms, Hamming Weight, inter-Hamming Distance (inter-HD) and intra-Hamming Distance (intra-HD) have been calculated to verify their randomness56. The Hamming weight is the number of non-zero symbol of a string, also equivalent of the Hamming distance with an all-zero string in the same length. As shown in Fig. 5a, the Hamming Weight distribution could be well fitted with Gaussian where the mean value is approximately in 50%, indicating an equal probability for the generation of “0” and “1”. The inter-HD is defined as the uniqueness between different devices and the intra-HD described the intrinsic variation from the same device. The inter-HD and intra-HD are all around 50% as shown in Fig. 5b-c, indicating the randomness of the bit generation (the calculation details could be found in experimental section). Note that the intra-HD is derived from 528 cycles from same device, where each key has 24 bits; and the inter-HD is derived from 26 devices and each device contains 48 cycles (in other words, 26 keys from different devices, each key has 48 bits). Combining the DDV, CCV and TTV could enhance the robustness of the cryptography keys, which include spatiotemporal variability together, as shown in Fig. 5d57. Those key lengths could be enough for the lightweight cryptography in embedded system or sensor networks. Note that the combination with periphery circuit could further improve the performance of the TRNG, e.g., the two-memristor-based structure could guarantee random number generation when one of the memristor are at fault stuck26; a combination of nonlinear-feedback shift register (NLFSR) could further improve the complexity and generation rate of the TRNG27. Fig. S6 exhibits three types of NLFSR, including Geffe generator, Massey-Rueppel multispeed generator, and Beth-Piper stop-and-go generator.
Fig. 5. Hamming Calculation and the cryptosystem. a, Hamming Weight. b, Intra-HD and c, Inter-HD of the CCV and DDV. d, The spatiotemporal variability including DDV, CCV and TTV as hardware primitive for random number generation. e-f, Illustration of a RSA-type cryptosystem, including key generation, message encryption and decryption, digital signature and authentication.
Implementation of the hardware primitives into cryptosystem can be a new fashion in both cryptology and electronic area. Here an example of hardware random numbers based asymmetric cryptosystem is shown in Fig. 5e. And the crypto key generation could be based on the RSA algorithm as shown in Fig. 5f. Note that, as comparison, a symmetric cryptosystem including text encryption and image encryption is shown in Fig. S5a1-c4 and Note II. Through a bit XOR method58, a message of “OLYMPIC” could be encrypted as “,/;.3* ” and an image of the device structure of current study could be successfully encrypted (if the RGB histogram can provide useful information, attackers could derive it and obtain information of the original image). Back to the RSA cryptosystem, through the prime number selector (as shown in Table S1 in Supplementary Materials), the random numbers have been transformed into p and q values, which are the key random numbers in the RSA system. As a result, the public key (N, E) and the private key (N, D) could be derived based on the hardware primitives. Then the demonstration of the private key and public key in information security is shown in Fig. 5e. Supposing that Bob wants to say “Hi Alice” to Alice, there are two paths to guaranteeing the information security with the private keys and public keys. In path 1, Bob encrypted the message by using the Alice's public key and sent to Alice; then Alice utilized her own private key to decrypt the message sent from Bob. Meanwhile, Bob needs to prove “Bob is Bob” because if an attacker Eve utilized Alice's public key to encrypt forged messages and sent them to Alice, then Alice could get wrong messages from Eve (in this case, Eve is the fake “Bob”). In this consideration, Bob needs to utilize his own private key to form a digital signature based on the one side hash function of the original message and send it to Alice. Because the digital signature includes the information of Bob's private key, then the message of path 2 can be proven to have come from the real Bob. To verify whether the message from path 1 does not contain counterfeit information, the message decrypted from Bob's side is also passed through Hash Function to compare with the decrypted messages from path 2. Using this approach, the information security and the authentication could be guaranteed.
Here, an example of how to generate the asymmetric random keys in RSA cryptosystem is shown. Supposing two simple prime number 5 and 11 are chosen for the RSA-based cryptosystem, a public key and private key of (55, 3) and (55, 27) could be generated. If Bob wants to deliver a message of “26” then a cyphertext of 16 is delivered to Alice. Alice could use the private key to decode. If an attacker Eve wants to decode the decoding process, she should find the D number and calculate the 2627 mod 55, which is 160059109085386090080713531498405298176. Thus, with only small prime numbers 5 and 11 already being able to generate this large product, choosing much larger prime numbers could further improve the robustness of the cryptosystem. For more information on the RSA algorithm, key generation process and calculation details can be found in Supplementary Materials Note I and Table S1. Based on the above analysis and calculation, the robustness of the cryptosystem is based on both the difficulty of solving discrete logarithms and the randomness of the memristive entropy source. Moreover, the intrinsic stochasticity of the spatiotemporal variability of the memristor provides temporally-changing, physically-unpredictable and machine-learning-attack-resilient primitives for random key generation, which also prevents the forward secrecy (FS) issue in the cryptography field. The FS is to ensure that the session key could not be compromised if the historical secrets have been compromised. Even if the attacker gets the session key one time, the previous and forward key generation is still highly secure. Moreover, the currently proposed memristive TRNG could be employed against the side channel attacks. As shown in Fig. S7, the physical power consumption cannot derive any useful information of the random numbers.

Conclusion

In this work, memristive spatiotemporal variation based on a graphene CBRAM has been comprehensively studied. Towards cryptographic key generation, three levels of analysis have been carried out: physical level, AI level, and random number level. On the physical-level analysis, a KMC simulation has been carried out to demonstrate the revolution of the filament during forming, Set and Reset, and the DDV and CCV are visualised. On the AI level, PCA, LSTM and SHAP value techniques have been utilized to investigate whether the intrinsic memristive stochastic parameters are truly random. The random-number-level analysis is based on Hamming distances calculation, which verifies the probability, stability, reproducibility and uniqueness of those random number based on the memristive primitives. Apart from the Set voltage distributions of the DDV and CCV, the RTN-based TTV has been investigated by kernel density map and time constant, which indicates equal chances of the upper and lower current levels. Merging the spatiotemporal variation including DDV, CCV and TTV as hardware primitive enhances the robustness of the cryptographic key generation. For practical application, Rivest-Shamir-Adleman (RSA) cryptosystem based on the memristive spatiotemporal variation has been demonstrated. As proven in the current study, the memristive spatiotemporal variability provides true randomness and also improves the robustness of the cryptosystem.

METHODS

Graphene-based CBRAM fabrication and characterization

Graphene layer was synthesized via chemical vapor deposition (the detailed growth parameters could be found in our previous reports) and transferred onto a 300 nm SiO2/Si substrate, assisted by polymethyl methacrylate (PMMA)59. Subsequently, photoresist spin coating, lithography, O2 plasma etching as well as acetone/isopropanol/deionized water cleaning were carried out to define the graphene back electrode. 50 nm Ni was thermally deposited on graphene electrode as a contacting pad (100 µm × 100 µm). Finally, 1.5 nm seeding layer of aluminium was deposed three times to naturally form AlOx as the resistive switching medium for the graphene-based CBRAM60. After all fabrication steps, electrical measurements were carried out in a B1500-Agilent semiconductor analyser.

Kinetic Monte Carlo simulation

The device structure is based on the TEM observation where top and bottom electrode is silver and graphene, and the switching medium is 6 nm of AlOx. Physical parameter settings could be found in Table S2 in Supplementary Materials.
Step 1: driven by the electric field, silver atoms oxidation into actions from the active electrode (forming) or filament (after forming),
M M ad n + + n e M bulk n + ,
where M represents silver atoms, M a d n + is the adsorbed cations, M b u l k n + is the cations in the bulk.
The oxidation probability can be described as:
P ox = f × exp ( ( E ox Δ φ ) / k B T ) ,
where f is the vibration frequency, Eox is the activation energy of oxidation, kB is the Boltzmann constant, T is the local temperature, and Δ φ is the barrier height reduction induced by electric field.
Step 2: cations transportation in electrolyte, with the probability of:
P h = f × exp ( ( E h Δ φ ) / k B T ) .
Step 3: cations reduction into silver atoms:
M n + + n e M ,
whose probability is:
P red = f × exp ( ( E red Δ φ ) / k B T ) ,
where [Math Processing Error]Ered is the activation barrier of reduction.
Step 4: silver atoms migration to the minimum energy locations. The migration probability can be described as:
P m = f × exp ( E m / k B T ) .
Note that the metal atoms migration takes place at the surface of the bottom electrode. After those steps, different conical- and dendrite-morphology conductive filaments of different devices and cycles are observed, as shown in Figs. 2 and S1.

Parameter selection for the LSTM predicting model

The parameters of the LSTM model were optimized utilizing the grid search technique and the optimizer Adam. The options for each parameter were: (a) training batch size: 8, 16, and 32; (b) dropout: 0, 0.1 and 0.3; (c) learning rate: 0.001 and 0.003; (d) hidden layers for the LSTM model: 3 to 8 hidden layers; (e) cells of the LSTM hidden layer: 4, 8, 16, 32, 64, and 128. In addition, each combination underwent four-fold cross-validation which was repeated 5 times to obtain the best results in this study. Finally, the optimized parameters of LSTM time step = 16 and time step = 32 were “training batch size: 16, dropout value: 0.1, learning rate: 0.003, the number of hidden layers: 3, cells of the LSTM hidden layer: 32” and “training batch size: 16, dropout value: 0.3, learning rate: 0.003, the number of hidden layers: 3, cells of the LSTM hidden layer: 8”, respectively.

Shapley additive explanations

In order to understand the importance of the input variables of each sub-model, we attempted the Shapley additive explanations (SHAP) analysis to describe the variable importance in this study. SHAP analysis, which is a cooperative game theory-based approach, is usually used to show the importance, a.k.a. contribution, of every input variable to the prediction of the model to increase the interpretability and transparency of the deep learning models.

Hamming Weight and Hamming Distance61

The Hamming Weight of a key can describe the bit uniformity, which is given as:
Uniformity = 1 n i = 1 n k i × 100 % ,
where ki refers to the kth bit of a n-bit key. In this study, n is 20 and k is 24. The ideal value is 50%, which indicates that the numbers of bits ‘1’ and bits ‘0’ in a key are equal.
The intra Hamming Distance (intra-HD) is used to describe the variation and denotes the difference among the keys generated from the same TRNG under different test conditions and cycles. The intra-HD is calculated by the equation:
Intra-HD = 2 m ( m 1 ) i = 1 m 1 j = i + 1 m HD ( K i , K j ) n × 100 % ,
where HD (Ki,Kj) is the HD between n-bit responses of the ith cycle and the jth cycle from a TRNG among m cycles, where currently n is 22 and m is 24. The ideal value is 0, which indicates that the TRNG can always produce identical keys with the same challenge. In the current work, the intra-HD is near 50%. It indicated the independency between different keys.
The inter Hamming Distance (inter-HD), which is used to describe the uniqueness, refers to the difference between the keys from difference devices. The inter-HD can be calculated by:
Inter-HD = 2 q ( q 1 ) i = 1 q 1 j = i + 1 q HD ( K i , K j ) n × 100 % ,
where HD (Ki,Kj) is the HD of the ith key and the jth key among q different n-bit keys. The ideal value is 50%. In this study, q is 26 and n is 48.

Key generation in RSA cryptosystem (detail explanation of Fig. 5f)

Step a: Obtain N from p*q, where the p and q are large prime numbers, taken from Table S1 based on spatiotemporal primitives.
Step b: Calculate Euler's totient function φ(N)= φ(p*q)= φ(p)*φ(q)=(p-1)(q-1).
Step c: Select e, where 1 < E < φ(N) meanwhile e should be coprime to φ(N).
Step d: Get d from φ ( N )
Step e: Form public key as (N, E) and private key as (N, D).

Encryption and decryption of RSA cryptosystem

Suppose m is the message that is going to be delivered, (N, E) and (N, D) are public key and private key. Then utilizing the RSA cryptosystem, cyphertext c of the m could be calculated by the following equation via public key (N, E):
c = E ( m ) = m E modN .
And, by utilizing the private key (N, D), the cyphertext c could be decoded to message m via the equation:
m = D ( c ) = c D modN .

MISCELLANEA

Supplementary materials Supplementary material associated with this article can be found, in the online version, at doi:10.1016/j.chip.2023.100040.
Acknowledgments This study was supported by grants from National Natural Science Foundation of China (62174008), Beijing Municipal Education Commission (KZ202110005001), the Ministry of Science and Technology, Taiwan, China (MOST 111-2119-M-492- 002-MBK, MOST 111-2622-8-182-001-TS1, MOST 109-2221-E-182-013-MY3, and MOST 110- 2221-E-182-043-MY3), and the Chang Gung Memorial Hospital (CORPD2J0073).
Declaration of Competing Interest The authors declare no competing interests.
1.
Chaudhury, P. et al. Asymmetric key based cryptographic algorithm using four prime numbers to secure message communication. A review on RSA algorithm. In 8th Annual Industrial Automation and Electromechanical Engineering Con- ference (IEMECON), 332-337 (IEEE, 2017). https://doi.org/10.1109/IEMECON.2017.8079618.

2.
Park, J., Lee, Y., Jeong, H. & Choi, S. Neural network physically unclonable func- tion: a trainable physically unclonable function system with unassailability against deep learning attacks using memristor array. Adv. Intell. Syst. 3, 2100111 (2021). https://doi.org/10.1002/aisy.202100111.

3.
Gao, B. et al. Concealable physically unclonable function chip with a memristor array. Sci. Adv. 8, eabn 7753 (2022). https://doi.org/10.1126/sciadv.abn7753.

4.
Oberoi, A., Dodda, A., Liu, H., Terrones, M. & Das, S. Secure electronics enabled by atomically thin and photosensitive two-dimensional memtransistors. ACS Nano 15, 19815-19827 (2021). https://doi.org/10.1021/acsnano.1c07292.

5.
Dodda, A. et al. Graphene-based physically unclonable functions that are re- configurable and resilient to machine learning attacks. Nat. Electron. 4, 364-374 (2021). https://doi.org/10.1038/s41928-021-00569-x.

6.
Yang, L. et al. In situ encryption: cryptographic key generation and in situ encryp- tion in one-transistor-one-resistor memristors for hardware security. Adv. Electron. Mater. 7, 2170012 (2021). https://doi.org/10.1002/aelm.202170012.

7.
Nili, H. et al. Hardware-intrinsic security primitives enabled by analogue state and nonlinear conductance variations in integrated memristors. Nat. Electron. 1, 197-202 (2018). https://doi.org/10.1038/s41928-018-0039-7.

8.
Dodda, A., Trainor, N., Redwing, J. M. & Das, S. All-in-one, bio-inspired, and low-power crypto engines for near-sensor security based on two- dimensional memtransistors. Nat. Commun. 13, 3587 (2022). https://doi.org/10.1038/s41467-022-31148-z.

9.
Mehonic, A. et al. Memristors—From in-memory computing, deep learning ac- celeration, and spiking neural networks to the future of neuromorphic and bio- inspired computing. Adv. Intell. Syst. 2, 2000085 (2020). https://doi.org/10.1002/aisy.202000085.

10.
Lanza, M. et al. Memristive technologies for data storage, computation, encryp- tion, and radio-frequency communication. Science 376, eabj 9979 (2022). https://doi.org/10.1126/science.abj9979.

11.
You, B. K. et al. Reliable memristive switching memory devices enabled by densely packed silver nanocone arrays as electric-field concentrators. ACS Nano 10, 9478-9488 (2016). https://doi.org/10.1021/acsnano.6b04578.

12.
Liu, Y., Gao, J., Wu, F., Tian, H. & Ren, T.-L. The origin of CBRAM with high linear- ity, on/offratio, and state number for neuromorphic computing. IEEE Trans. Elec- tron Devices 68, 2568-2571 (2021). https://doi.org/10.1109/TED.2021.3065013.

13.
Zhao, X. et al. Breaking the current-retention dilemma in cation-based resis- tive switching devices utilizing graphene with controlled defects. Adv. Mater. 30, 1705193 (2018). https://doi.org/10.1002/adma.201705193.

14.
Zhao, X. et al. Confining cation injection to enhance CBRAM performance by nanopore graphene layer. Small 13, 1603948 (2017). https://doi.org/10.1002/smll.201603948.

15.
Liu, Y., Yang, K., Wang, X., Tian, H. & Ren, T.-L. Lower power, better uniformity, and stability CBRAM enabled by graphene nanohole interface engineering. IEEE Trans. Electron Devices 67, 984-988 (2020). https://doi.org/10.1109/TED.2020.2968731.

16.
Lee, J., Du, C., Sun, K., Kioupakis, E. & Lu, W. D. Tuning ionic transport in mem- ristive devices by graphene with engineered nanopores. ACS Nano 10, 3571-3579 (2016). https://doi.org/10.1021/acsnano.5b07943.

17.
Lv, S., Liu, J. & Geng, Z. Application of memristors in hardware security: A current state-of-the-art technology. Adv. Intell. Syst. 3, 2000127 (2021). https://doi.org/10.1002/aisy.202000127.

18.
Rajendran, G., Banerjee, W., Chattopadhyay, A. & Aly, M. M. S. Application of resistive random access memory in hardware security: A review. Adv. Electron. Mater. 7, 2100536 (2021). https://doi.org/10.1002/aelm.202100536.

19.
Pang, Y., Gao, B., Lin, B., Qian, H. & Wu, H. Memristors for hardware security ap- plications. Adv. Electron. Mater. 5, 1800872 (2019). https://doi.org/10.1002/aelm.201800872.

20.
Carboni, R. & Ielmini, D. Stochastic memory devices for security and computing. Adv. Electron. Mater. 5, 1900198 (2019). https://doi.org/10.1002/aelm.201900198.

21.
James, A. P. An overview of memristive cryptography. Eur. Phys. J. Spec. Top. 228, 2301-2312 (2019). https://doi.org/10.1140/epjst/e2019-900044-x.

22.
Du, N., Schmidt, H. & Polian, I. Low-power emerging memristive designs towards secure hardware systems for applications in internet of things. Nano Mater. Sci. 3, 186-204 (2021). https://doi.org/10.1016/j.nanoms.2021.01.001.

23.
Balatti, S., Ambrogio, S., Wang, Z. & Ielmini, D. True random number genera- tion by variability of resistive switching in oxide-based devices. IEEE J. Emerg. Sel. Top. Circuits Syst. 5, 214-221 (2015). https://doi.org/10.1109/JETCAS.2015.2426492.

24.
Wei, Z. et al. True random number generator using current difference based on a fractional stochastic model in 40-nm embedded ReRAM. 2016 IEEE Inter- na- tional Electron Devices Meeting (IEDM), 4.8.1-4.8.4 (IEEE, 2016). https://doi.org/10.1109/IEDM.2016.7838349.

25.
Jiang, H. et al. A novel true random number generator based on a stochas- tic diffusive memristor. Nat. Commun. 8, 882 (2017). https://doi.org/10.1038/s41467-017-00869-x.

26.
Woo, K. S. et al. A true random number generator using threshold-switching- based memristors in an efficient circuit design. Adv. Electron. Mater. 5, 1800543 (2019). https://doi.org/10.1002/aelm.201800543.

27.
Woo, K. S. et al. A combination of a volatile-memristor-based true random- number generator and a nonlinear-feedback shift register for high-speed en- cryption. Adv. Electron. Mater. 6, 1901117 (2020). https://doi.org/10.1002/aelm.201901117.

28.
Woo, K. S. et al. A high-speed true random number generator based on a Cu x Te 1 -x diffusive memristor. Adv. Intell. Syst. 3, 2100062 ( 2021). https://doi.org/10.1002/aisy.202100062.

29.
Kim, G. et al. Self-clocking fast and variation tolerant true random number gen- erator based on a stochastic mott memristor. Nat. Commun. 12, 2906 (2021). https://doi.org/10.1038/s41467-021-23184-y.

30.
Wen, C. et al. Advanced data encryption using 2D materials. Adv. Mater. 33, 2100185 (2021). https://doi.org/10.1002/adma.202100185.

31.
Liu, B. et al. Bi 2 O 2 Se-based true random number generator for security ap- plications. ACS Nano 16, 6847-6857 (2022). https://doi.org/10.1021/acsnano.2c01784.

32.
Liu, B. et al. Dimensionally anisotropic graphene with high mobility and a high on-offratio in a three-terminal RRAM device. Mater. Chem. Front. 4, 1756-1763 (2020). https://doi.org/10.1039/D0QM00152J.

33.
Illarionov, Y. Y. et al. Insulators for 2D nanoelectronics: the gap to bridge. Nat. Commun. 11, 3385 (2020). https://doi.org/10.1038/s41467-020-16640-8.

34.
Yuan, F. et al. Real-time observation of the electrode-size-dependent evolution dynamics of the conducting filaments in a SiO 2 layer. ACS Nano 11, 4097-4104 (2017). https://doi.org/10.1021/acsnano.7b00783.

35.
Wang, C. et al. Conduction mechanisms, dynamics and stability in ReRAMs. Mi- croelectron. Eng. 187-188, 121-133 (2018). https://doi.org/10.1016/j.mee.2017.11.003.

36.
Zhu, X., Lee, S. H. & Lu, W. D. Nanoionic resistive-switching devices. Adv. Elec- tron. Mater. 5, 1900184 (2019). https://doi.org/10.1002/aelm.201900184.

37.
Lee, J. & Lu, W. D. On-demand reconfiguration of nanomaterials: When electron- ics meets ionics. Adv. Mater. 30, 1702770 (2018). https://doi.org/10.1002/adma.201702770.

38.
Alonso, F. J., Maldonado, D., Aguilera, A. M. & Roldán, J. B. Memristor variabil- ity and stochastic physical properties modeling from a multivariate time series ap- proach. Chaos Solit. Fractals 143, 110461 (2021). https://doi.org/10.1016/j.chaos.2020.110461.

39.
Gao, L., Ren, Q., Sun, J., Han, S.-T. & Zhou, Y. Memristor modeling: challenges in theories, simulations, and device variability. J. Mater. Chem. C 9, 16859-16884 (2021). https://doi.org/10.1039/D1TC04201G.

40.
Liu, B. et al. Bi 2 O 2 Se-based memristor-aided logic. ACS Appl. Mater. Interfaces 13, 15391-15398 (2021). https://doi.org/10.1021/acsami.1c00177.

41.
Zhao, Y. D. et al. Atomic Monte-Carlo simulation for CBRAM with various fil- ament geometries. In International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 153-156 (IEEE, 2016). https://doi.org/10.1109/SISPAD.2016.7605170.

42.
Qin, S. et al. Atomistic study of dynamics for metallic filament growth in conductive-bridge random access memory. Phys. Chem. Chem. Phys. 17, 8627-8632 (2015). https://doi.org/10.1039/C4CP04903A.

43.
Wang, Z. et al. Resistive switching memristor: on the direct observation of physical nature of parameter variability. ACS Appl. Mater. Interfaces 14, 1557-1567 (2022). https://doi.org/10.1021/acsami.1c19364.

44.
Sun, W. et al. Understanding memristive switching via in situ characterization and device modeling. Nat. Commun. 10, 3453 (2019). https://doi.org/10.1038/s41467-019-11411-6.

45.
Baeumer, C. et al. Subfilamentary networks cause cycle-to-cycle variability in memristive devices. ACS Nano 11, 6921-6929 (2017). https://doi.org/10.1021/acsnano.7b02113.

46.
Lee, J.-H., Lim, D.-H., Jeong, H., Ma, H. & Shi, L. Exploring cycle-to-cycle and device-to-device variation tolerance in MLC storage-based neural network train- ing. IEEE Trans. Electron Devices 66, 2172-2178 (2019). https://doi.org/10.1109/TED.2019.2906249.

47.
Choi, S., Shin, J. H., Lee, J., Sheridan, P. & Lu, W. D. Experimental demonstration of feature extraction and dimensionality reduction using memristor networks. Nano Lett. 17, 3113-3118 (2017). https://doi.org/10.1021/acs.nanolett.7b00552.

48.
Lin, A. S. et al. A process-aware memory compact-device model using long- short term memory. IEEE Access 9, 3126-3139 (2021). https://doi.org/10.1109/ACCESS.2020.3047491.

49.
Li, C. et al. Long short-term memory networks in memristor crossbar arrays. Nat. Mach. Intell. 1, 49-57 (2019). https://doi.org/10.1038/s42256-018-0001-4.

50.
Kim, S. et al. Experimental demonstration of a second-order memristor and its ability to biorealistically implement synaptic plasticity. Nano Lett. 15, 2203-2211 (2015). https://doi.org/10.1021/acs.nanolett.5b00697.

51.
Wali, A., Ravichandran, H. & Das, S. A machine learning attack resilient true random number generator based on stochastic programming of atomically thin transistors. ACS Nano 15, 17804-17812 (2021). https://doi.org/10.1021/acsnano.1c05984.

52.
Sánta, B. et al. Universal 1/ f type current noise of Ag filaments in redox-based memristive nanojunctions. Nanoscale 11, 4719-4725 (2019). https://doi.org/10.1039/C8NR09985E.

53.
Sánta, B. et al. Noise tailoring in memristive filaments. ACS Appl. Mater. Interfaces 13, 7453-7460 (2021). https://doi.org/10.1021/acsami.0c21156.

54.
González-Cordero, G. et al. Neural network based analysis of random telegraph noise in resistive random access memories. Semicond. Sci. Technol. 35, 025021 (2020). https://doi.org/10.1088/1361-6641/ab6103.

55.
Li, X. et al. Random telegraph noise in metal-oxide memristors for true random number generators: a materials study. Adv. Funct. Mater. 31, 2102172 (2021). https://doi.org/10.1002/adfm.202102172.

56.
Lin, B. et al. A highly reliable RRAM physically unclonable function utilizing post- process randomness source. IEEE J. Solid-State Circ. 56, 1641-1650 (2021). https://doi.org/10.1109/JSSC.2021.3050295.

57.
Kim, J. H. et al. Nanoscale physical unclonable function labels based on block copolymer self-assembly. Nat. Electron. 5, 433-442 (2022). https://doi.org/10.1038/s41928-022-00788-w.

58.
Song, Y., Wu, Q., Wang, X., Wang, C. & Miao, X. Two memristors-based XOR logic demonstrated with encryption/decryption. IEEE Electron Device Lett. 42, 1398-1401 (2021). https://doi.org/10.1109/LED.2021.3102678.

59.
Liu, B. et al. Programmable synaptic metaplasticity and below femtojoule spiking energy realized in graphene-based neuromorphic memristor. ACS Appl. Mater. Interfaces 10, 20237-20243 (2018). https://doi.org/10.1021/acsami.8b04685.

60.
Liu, B. et al. A fluorographene-based synaptic transistor. Adv. Mater. Technol. 4, 1900422 (2019). https://doi.org/10.1002/admt.201900422.

61.
Gao, Y., Ranasinghe, D. C., Al-Sarawi, S. F., Kavehei, O. & Abbott, D. Memristive crypto primitive for building highly secure physical unclonable functions. Sci. Rep. 5, 12785 (2015). https://doi.org/10.1038/srep12785.

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