Integrated Circuits and Systems >

2025 , Vol. 2 >Issue 1: 13 - 21

DOI: https://doi.org/10.23919/ICS.2025.3553458

Special Issue Papers

A Sub-5 ppm/°C Bandgap Voltage Reference With Dual Source-Sink Current Compensation

  • HANRU YANG ,
  • TIANRUI LYU ,
  • XIAO HUANG ,
  • JIANPING GUO
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  • Sun Yat-sen University, Guangzhou 510275, China
XIAO HUANG (e-mail: )
JIANPING GUO (e-mail: )

JIANPING GUO (Senior Member, IEEE)

Received date: 2024-12-31

  Revised date: 2025-02-17

  Accepted date: 2025-03-15

  Online published: 2025-10-22

Supported by

Industrial Core and Key Technique Research Project of Zhuhai under Grant(2320004002564)

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Abstract

This work presents a bandgap voltage reference (BGR) with source-sink dual current compensation achieving a low temperature coefficient (TC) over the automotive temperature range from −40 to 125 °C. The two compensation currents are the inverted-V current (IinvV) and the high-low temperature linear current (IHLT), which appear in the form of sourcing and sinking currents, respectively. This design introduces an inverted-V current to mitigate the degradation of the compensation effect caused by temperature range drifts. By exploiting the characteristics of IinvV and IHLT exhibiting the same drift trend, the dual current compensation achieves the compensation performance over the entire automotive temperature range while mitigating the impact of temperature range drifts, thereby optimizing the overall compensation effect. The measured results show that it achieves the best TC of 2.0 ppm/°C and an average consumption current of 44 μA at room temperature. Moreover, the linear sensitivity (LS) is 0.04%/V and power supply rejection (PSR) is −60 dB at 1 Hz at room temperature.

Key words： Bandgap voltage reference; source-sink current compensation; low temperature coefficient; battery management integrated circuits

Cite this article

HANRU YANG , TIANRUI LYU , XIAO HUANG , JIANPING GUO . A Sub-5 ppm/°C Bandgap Voltage Reference With Dual Source-Sink Current Compensation[J]. Integrated Circuits and Systems, 2025 , 2(1) : 13 -21 . DOI: 10.23919/ICS.2025.3553458

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