Integrated Circuits and Systems >

2025 , Vol. 2 >Issue 1: 28 - 35

DOI: https://doi.org/10.23919/ICS.2025.3547674

Special Issue Papers

Thermal Stress Analysis and Key Influencing Factors for the EMIB in Chiplet Packaging

  • YAN ZHOU 1 ,
  • JUN WANG , 1, 2
Expand
  • 1 Department of Materials Science, Fudan University, Shanghai 200437, China
  • 2 Yiwu Research Institute of Fudan University, Yiwu 322000, P. R. China
JUN WANG (e-mail: ).

YAN ZHOU (Graduate Student Member, IEEE)

Received date: 2025-01-01

  Revised date: 2025-02-14

  Accepted date: 2025-02-27

  Online published: 2025-10-22

Supported by

National Natural Science Foundation of China under Grant(61774044)

Ministry of Education (MOE) Innovation Platform

Fold

Abstract

This study presents a comprehensive thermal stress analysis of critical components in an embedded multi-die interconnect bridge (EMIB) within a chiplet package using finite element analysis (FEA). We systematically evaluated key design parameters—including bump diameter-to-pitch ratios, bump distribution patterns, EMIB thickness, number of EMIBs, and aspect ratios—to assess their impact on stresses. An ABAQUS-based FEA model was used to simulate thermal loading with a 165 °C temperature increase. The results indicate that a bump diameter-to-pitch ratio of 0.3 optimizes stress distribution, while a peripheral bump arrangement is superior in stress reduction compared to other patterns. Thinner EMIBs linearly reduce maximum principal stress, whereas multiple EMIBs and aspect ratio variations have minimal effects. These findings offer practical guidelines for optimizing EMIB design in chiplet packages, emphasizing the importance of bump geometry, distribution patterns, and EMIB thickness for improved reliability.

Key words： 3-D integration; chiplet packaging; embedded multi-die interconnect bridge (EMIB); thermo-mechanical reliability; thermal stress analysis; copper micro-bumps

Cite this article

YAN ZHOU , JUN WANG . Thermal Stress Analysis and Key Influencing Factors for the EMIB in Chiplet Packaging[J]. Integrated Circuits and Systems, 2025 , 2(1) : 28 -35 . DOI: 10.23919/ICS.2025.3547674

References

Publishing order | Descend order by publishing year | Descend order by cited within
[1]
T. Vijayaraghavan et al., “Design and analysis of an APU for exascale computing,” in Proc. IEEE Int. Symp. High Perform. Comput. Archit., Feb. 2017, pp. 85-96.

[2]
D. Stow, Y. Xie, T. Siddiqua, and G. H. Loh, “Cost-effective design of scalable high-performance systems using active and passive interposers,” in Proc. IEEE/ACMInt. Conf. Comput.-Aided Des., Irvine, CA, USA, 2017, pp. 728-735, doi: 10.1109/ICCAD.2017.8203849.

[3]
S. Naffziger, K. Lepak, M. Paraschou, and M. Subramony, “2.2 AMD chiplet architecture for high-performance server and desktop products,” in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2020, pp. 44-45.

[4]
R. Agarwal et al., “3D packaging for heterogeneous integration,” in Proc. IEEE 72nd Electron. Compon. Technol. Conf., May 2022, pp. 1103-1107.

[5]
R. Munoz, “Furthering Moore’s law integration benefits in the chiplet era,” IEEE Des. Test, vol. 41, no. 1, pp. 81-90, Feb. 2024.

[6]
G. H. Loh and R. Swaminathan, “The next era for chiplet innovation,” in Proc. Des., Automat. Test Europe Conf. Exhib., Apr. 2023, pp. 1-6.

[7]
D. Das Sharma and R. V.Mahajan, “Advanced packaging of chiplets for future computing needs,” Nature Electron., vol. 7, no. 6, pp. 425-427, Jun. 2024.

[8]
D. Das Sharma, G. Pasdast, S. Tiagaraj, and K. Aygün, “Highperformance, power-efficient three-dimensional system-in-package designs with universal chiplet interconnect express,” Nature Electron., vol. 7, no. 3, pp. 244-254, Mar. 2024.

[9]
C.-C. Wang et al., “Creative design and structure applied to chiplets packaging,” in Proc. IEEE 73rd Electron. Compon. Technol. Conf., May 2023, pp. 1353-1358.

[10]
I. Cutress, “Intel’s interconnected future: Combining chiplets, EMIB, and foveros,” AnandTech, Apr. 17, 2019. Accessed:Dec. 17, 2023.[Online]. Available: https://www.anandtech.com/show/14211/intelsinterconnected-future-chipslets-emib-foveros

[11]
G. Duan, Y. Kanaoka, R. McRee, B. Nie, and R. Manepalli, “Die embedding challenges for EMIB advanced packaging technology,” in Proc. IEEE 71st Electron. Compon. Technol. Conf., Jun. 2021, pp. 1-7.

[12]
R. Mahajan et al., “Embedded multi-die interconnect bridge (EMIB)- A high density, high bandwidth packaging interconnect,” in Proc. IEEE 66th Electron. Compon. Technol. Conf., May 2016, pp. 557-565.

[13]
R. Viswanath, A. Chandrasekhar, S. Srinivasan, Z. Qian, and R. Mahajan, “Heterogeneous SoC integration with EMIB,” in Proc. IEEE Elect. Des. Adv. Packag. Syst. Symp., Dec. 2018, pp. 1-3.

[14]
Y. Cho, K. Lee, K. Hwang, H. Lee, Y. Im, and M. Kim, “Thermal perspective design analysis of 3D stacked chip integrated by TSV, Micro-bump and TMV with SOC,” in Proc. 21st IEEE Intersociety Conf. Thermal Thermomechanical Phenomena Electron. Syst., May 2022, pp. 1-6.

[15]
P. Gupta et al., “Reference thermal chips for 2D and 3D co-packaging process development,” in Proc. IEEE 73rd Electron. Compon. Technol. Conf., Orlando, FL, USA, May 2023, pp. 2160-2165.

[16]
Y. Zhang, J. Wang, and S. Yu, “Thermal stress analysis and design guidelines for through silicon via structure in 3D IC integration,” in Proc. 19th Int. Conf. Electron. Packag. Technol., Aug. 2018, pp. 883-885.

[17]
T. -Y. Chen, D. -L. Chen, F. Chiu, C. -C. Wang, and C. -P. Hung, “Investigation into the impact of layout design on thermal performance in embedded-die packages,” in Proc. Int. Conf. Electron. Packag., Toyama, Japan, 2024, pp. 249-250, doi: 10.23919/ICEP61562.2024.10535653.

[18]
R. Mahajan et al., “Embedded multidie interconnect bridge—A localized, high-density multichip packaging interconnect,” IEEE Trans. Compon. Packag. Manuf. Technol., vol. 9, no. 10, pp. 1952-1962, Oct. 2019.

Options
Outlines

/

〈 〉