ZHONGFENG WANG received the B.E. and M.S. degrees from the Deparment of Automation, Tsinghua University, Beijing, China, in 1988 and 1990, respectively, and the Ph.D. degree from the University of Minnesota, Minneapolis, MN, USA, in 2000. He was with Oregon State University and National Semiconductor Corporation. From 2007 to 2016, he was a Technical Director with Broadcom Corporation, California. Since 2016, he has been a Distinguished Professor with Nanjing University, Nanjing, China. In 2023, he started serving as the Dean of the School of Integrated Circuits, Sun Yat-sen University, Guangzhou, China. He is a world-recognized expert on Low-Power High-Speed VLSI Design for Signal Processing Systems. He has authored or coauthored more than 400 technical papers with numerous best paper awards received from the IEEE technical societies, including the Circuits and Systems Society 2007 and 2025 VLSI Transactions Best Paper Award. He has edited one VLSI book and held more than 50 U.S. and China granted patents. His research interests are in the area of optimized VLSI design for digital communications and Deep Learning. In the current record, he has had many papers ranking among top 25 most (annually) downloaded manuscripts in IEEE Transactions on VLSI Systems. In the past, he was an Associate Editor for IEEE Transactions on TCAS-I, T-CAS-II, and T-VLSI for many terms. He was also the TPC member and various chairs for tens of international conferences.Moreover, he has contributed significantly to the industrial standards. So far, his technical proposals have been adopted by more than 20 international networking standards. In 2015, he was elevated to the Fellow of IEEE for contributions to VLSI design and implementation of FEC coding.