Integrated Circuits and Systems >

2025 , Vol. 2 >Issue 3: 102 - 109

DOI: https://doi.org/10.23919/ICS.2025.3567939

Regular Papers

A High-Resistance SOT Device Based Computing-in-Memory Macro With High Sensing Margin and Multi-Bit MAC Operations for AI Edge Inference

  • JUNZHAN LIU 1, 2 ,
  • JINYAO MI 1, 2 ,
  • YANG LIU 3 ,
  • LIANG ZHANG 1, 2 ,
  • HE ZHANG 1, 2 ,
  • WANG KANG , 1, 2
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  • 1 National Key Laboratory of Spintronics, Hangzhou International Innovation Institute, Beihang University, Hangzhou 311115, China
  • 2 School of Integrated Circuit Science and Engineering, Beihang University, Beijing 100191, China
  • 3 School of Electronic Information Engineering, Beihang University, Beijing 100191, China
WANG KANG (e-mail: ).

Junzhan Liu and Jinyao Mi contributed equally to this work.

WANG KANG (Senior Member, IEEE)

Received date: 2024-12-20

  Revised date: 2025-03-03

  Accepted date: 2025-04-30

  Online published: 2025-10-22

Supported by

Beijing MSTC Program under Grant(Z231100007423019)

Beijing Natural Science Foundation under Grant(L223004)

Natural Science Foundation of China under Grant(62274008)

Research Funding of Hangzhou International Innovation Institute of Beihang University under Grant(2024KQ157)

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Abstract

Computing-in-memory (CIM) offers a promising solution to the memory wall issue. Magnetoresistive random-access memory (MRAM) is a favored medium for CIM due to its non-volatility, high speed, low power, and technology maturity. However, MRAM has continuously encountered the challenge of an insufficient high-resistance state (HRS) to low-resistance state (LRS) ratio, which affects the result accuracy of CIM. In this paper, based on SOT devices, we propose a 5T2M bit-cell structure that increases the high-to-low current ratio by modulating the sub-threshold operation region. Besides, by jointly using high-resistance devices (M_ level), the power consumption of the bit-cell array can be significantly reduced. Simultaneously, we have designed a compatible multi-bit implementation and macro architecture to support AI edge inference acceleration. This work was simulated under a 40-nm foundry process and a physically verified SOT-MTJ model. The results show that under the same high-to-low resistance ratio, a 52.6× high-to-low current ratio can be achieved, along with a 38.6%-98% bit-cell array power reduction.

Key words： Computing-in-memory; SOT-MRAM; HRS/LRS ratio; multi-bit; artificial intelligence

Cite this article

JUNZHAN LIU , JINYAO MI , YANG LIU , LIANG ZHANG , HE ZHANG , WANG KANG . A High-Resistance SOT Device Based Computing-in-Memory Macro With High Sensing Margin and Multi-Bit MAC Operations for AI Edge Inference[J]. Integrated Circuits and Systems, 2025 , 2(3) : 102 -109 . DOI: 10.23919/ICS.2025.3567939

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