Integrated Circuits and Systems >

2025 , Vol. 2 >Issue 3: 139 - 148

DOI: https://doi.org/10.23919/ICS.2025.3563318

Regular Papers

A Novel Power and Area Efficient Digital Beamformer Architecture Using Bit-Stream Processing with MASH △∑ Modulators

  • TAO ZHONG 1, 2 ,
  • YUEKANG GUO 2 ,
  • JING JIN , 2 ,
  • JIANJUN ZHOU 2
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  • 1 State Key Laboratory of Micro-Nano Engineering Science, Shanghai Jiao Tong University, Shanghai 200240, China
  • 2 School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai 200240, China
JING JIN (e-mail: ).

TAO ZHONG was born in Shanghai, China, in 1995. He received the M.S. degree in electrical engineering from the Eindhoven University of Technology, Eindhoven, The Netherlands, in 2020. He is currently working toward the Ph.D. degree in electronic science and technology with the School of Electronic, Information, and Electrical Engineering, Shanghai Jiao Tong University, Shanghai, China. His current research focuses on noise shaping analog-to-digital converters.

YUEKANG GUO was born in Fuzhou, Jiangxi, China, in 1995. He received the B.S. degree in electronics engineering from the Harbin Institute of Technology, Harbin, China, in 2017, and the Ph.D. degree from Shanghai Jiao Tong University, Shanghai, China, in 2023. He is currently an Assistant Professor with the Center for Analog/RF Integrated Circuits, Department of Micro/Nano Electronics, Shanghai Jiao Tong University. His research focuses on noise shaping ADCs. He was a Reviewer for IEEE JOURNAL OF SOLID-STATE CIRCUITS and IEEE TRANSACTIONS ON CIRCUITS AND SYSTEM I.

JING JIN was born in Nantong, Jiangsu, China, in 1983. She received the B.S. degree in electronics information engineering from the Nanjing University of Science and Technology, Nanjing, China, in 2005, and the Ph.D. degree in electronics science and technique from Shanghai Jiao Tong University, Shanghai, China, in 2012. She is currently a Professor with the Center for Analog/RF Integrated Circuits, Department of Micro/Nano Electronics, Shanghai Jiao Tong University, Shanghai. Her research focuses on RF/mixed-signal integrated circuit design.

JIANJUN ZHOU (Senior Member, IEEE) received the B.S. degree in electronic engineering from Shanghai Jiao Tong University, Shanghai, China, in 1991, and the Ph.D. degree in electrical and computer engineering from Oregon State University, Corvallis, OR, USA, in 1998. While working with Qualcomm from 1998 to 2006, he led the efforts on developing the world’s first CMOS CDMA Tx IC and the world’s first CMOS CDMA Transceiver IC, each with a shipment exceeding 100 million units. In 2007, he became a Professor with Shanghai Jiao Tong University, and the Director of the Center for Analog/RF Integrated Circuits. His current research interests include mixedsignal/ analog/RF IC designs for wireless communications and high-speed wireline communications. He has authored or coauthored more than 100 peer-reviewed technical papers and holds more than 20 IC design patents. He was the recipient of ISSCC Beatrice Winner Award in 1998 and Shanghai Grand Prize for Progress in Science and Technology in 2016.

Received date: 2025-01-31

  Revised date: 2025-03-28

  Accepted date: 2025-04-13

  Online published: 2025-10-22

Supported by

Chinese National Natural Science Foundation under Grant 62431016 and Grant(62122051)

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Abstract

The evolution of 5G and beyond wireless networks has intensified the demand for millimeterwave technology to support high-throughput applications. This paper introduces a novel energy-efficient digital beamforming receiver architecture that integrates multi-stage noise-shaping (MASH) delta-sigma modulators (DSMs) with bit-stream processing (BSP), effectively addressing the significant propagation losses and dynamic electromagnetic interference associated with millimeter-wave (mm-wave) systems. The novel architecture achieves enhanced dynamic range without increasing signal bit-width, thereby ensuring low power consumption and a compact design. Unlike traditional analog and hybrid beamforming methods, the proposed approach utilizes digital-domain processing for precise beamforming, simplified local oscillator networks, and improved integration. System-level simulations with a 9-antenna beamforming receiver array demonstrate the architecture’s capability for accurate beamforming across angles from 30° to 150° and effective dual-target detection. Furthermore, the P2S-BSP architecture reduces digital circuitry area by 50% compared to previous implementations while maintaining energy efficiency. These advancements highlight the proposed architecture as a scalable solution for future mm-wave applications, including intelligent transportation systems, radar, and high-density mobile networks.

Key words： Bit-stream processing; digital beamforming; multi-stage noise-shaping; delta-sigma modulator

Cite this article

TAO ZHONG , YUEKANG GUO , JING JIN , JIANJUN ZHOU . A Novel Power and Area Efficient Digital Beamformer Architecture Using Bit-Stream Processing with MASH △∑ Modulators[J]. Integrated Circuits and Systems, 2025 , 2(3) : 139 -148 . DOI: 10.23919/ICS.2025.3563318

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