SPHINCS+ is a hash-based digital signature scheme that has been selected for post-quantum cryptography(PQC) standardization announced by the U.S. National Institute of Standards and Technology (NIST) in 2022. Although SPHINCS+ offers significant security against quantum attacks, its relatively slow computation times present a major obstacle to its practical deployment. To address this challenge, improving the computational efficiency of SPHINCS+ becomes a critical task. The cryptographic operations in SPHINCS+ rely on tweakable hash functions, with various hash algorithms available for selection. Among these, SHA-3 stands out as a widely adopted and NIST-standardized hash function, making it a preferred choice for implementation in SPHINCS+. In this work, we propose a dedicated coprocessor that integrates a SHA-3 accelerator along with its associated peripheral structure. This coprocessor is designed to extend the RISC-V instruction set by incorporating seven custom instructions, enabling efficient software-hardware co-acceleration. Furthermore, we investigate the parallelizable components within SPHINCS+, specifically the FORS and WOTS+ Algorithms, to identify means for optimization. By leveraging thread-level parallelism through multi-core programming, we achieve significant improvements in performance. To validate the design, synthesis is performed using TSMC 28-nm CMOS technology at 800 MHz. Compared to the benchmark results from the ARM Cortex-M4 processor, our approach achieves an impressive 23.1× speedup in the overall single-core performance of SPHINCS+, with an additional 3.4× speedup for the verification process by utilizing multi-core acceleration.