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| Design for Silicon Debug of Integrated Circuit by Reusing Test Logic |
| ZHANG Ming, GAO Jun, ZHANG Min-Xuan |
| (College of Computer, National University of Defense Technology， Changsha 410073, China) |
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Abstract Test logic is often reused by silicon debug during design stage of IC. Based on reusing test logic, two improved structures for silicon debug were proposed, one is that scanning registers in short chains to speedup accesses of focused registers, another is that adding asynchronous debug ports for memory build-in self-test (MBIST) controller, which accelerates accesses of static memory and reduces difficulties of physical design. The experiment reflects that the proposed structure decreases difficulty and complexity of the corresponding software extremely at little extra resources cost, and makes debug operations faster.
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Received: 12 May 2012
Published: 30 January 2013
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| [1] |
SUN Yan, SONG Chao, LI Tie-Jun, ZHANG Min-Xuan. A 3D Stacking Technology Based Reliable Cache Architecture[J]. J. Shanghai Jiaotong Univ.(Sci.) , 2013, 47(01): 65-69. |
| [2] |
SONG Zhen-Long, LI Qiong, XU Wei-Xia, LI Jin-Wen, LIU Guang-Ming. Realization and Design of a Hybrid Storage System in High Performance Computing[J]. J. Shanghai Jiaotong Univ.(Sci.) , 2013, 47(01): 113-117. |
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