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| A 3D Stacking Technology Based Reliable Cache Architecture |
| SUN Yan, SONG Chao, LI Tie-Jun, ZHANG Min-Xuan |
| (College of Computer, National University of Defense Technology, Changsha 410073, China) |
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Abstract Focused on soft error issue in 3D integrated circuits, this paper analyzed particles tracks and characters when highenergy particles get into 3D stacking chips, and then presented a kind of 3D stacking technologybased reliable Cache architecture R3DCache after analyzing soft error vulnerability of each component of Caches. The R3DCache can greatly reduce error rate with little area and performance overheads. The analysis results show that the proposed structure can bring down soft error rate of Caches to 5% of original one with 0.52% to 4.17% area overhead, while the performance overhead can be ignored.
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Received: 29 June 2012
Published: 30 January 2013
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| [1] |
ZHANG Ming, GAO Jun, ZHANG Min-Xuan. Design for Silicon Debug of Integrated Circuit by Reusing Test Logic[J]. J. Shanghai Jiaotong Univ.(Sci.) , 2013, 47(01): 55-59. |
| [2] |
SONG Zhen-Long, LI Qiong, XU Wei-Xia, LI Jin-Wen, LIU Guang-Ming. Realization and Design of a Hybrid Storage System in High Performance Computing[J]. J. Shanghai Jiaotong Univ.(Sci.) , 2013, 47(01): 113-117. |
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