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| A Synthesizable Pseudo-Random Functional Verification Method for Cache |
| ZHANG Jian-Min, ZHANG Jun, XIA Jun, PANG Zheng-Bin, XU Wei-Xia |
| (College of Computer, National University of Defense Technology, Changsha 410073, China) |
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Abstract For the Cache in the microprocessors, a synthesizable pseudo-random functional verification method was proposed. This method was applied in the real chips, and was compared with the pseudo-random verification method on software simulation in performance. The results show that the method is faster by about three orders of magnitude, and can find more bugs in the designs in comparison to the pseudo-random verification method on software simulation.
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Received: 17 May 2012
Published: 30 January 2013
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