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Implementing hardware primitives based on memristive spatiotemporal variability into cryptography applications

Bo Liu, Yudi Zhao, YinFeng Chang, Han Hsiang Tai, Hanyuan Liang, Tsung-Cheng Chen, Shiwei Feng, Tuo-Hung Hou, Chao-Sung Lai

Chip, 2023, 2(1): 100040-12. DOI: 10.1016/j.chip.2023.100040

Fig. 2. Kinetic Monte Carlo simulation of graphene CBRAM for visualising DDV and CCV. a, Schematics of the device structure and the holistic filament revolution; including p1: anode oxidation, p2: cation hopping, p3: cation reduction and deposition on cathode, p4: electron emission, p5: electron hopping, p6: electron adsorption, p7 cation and electron reduction. b, Electric field alter the migration barrier of cation and electron; and the reduction of the cation and electron. c, Filament morphology of four different devices after forming process. d, Filament morphology of 4 cycles of Set and Reset, including the first forming process.

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Fig. 1. Spatiotemporal variability of memristor. a, The illustration of DDV and the device structure. b, The typical resistive switching IV curves of memristor, where the CC is set as 100 µA to prevent hard breakdown and overshooting, more results of CCV could be found in Fig. 3. c, Energy diagram showing charge transfer of the redox reaction between Ag atom in the filaments and Ag ion dissolved in the AlOx layer; those effects differ from device to device and cycle to cycle, indicating spatiotemporal variability. d, The T2T variability includes the RTN signals, d1-d3 exhibit the current fluctuation under different V_BG, ranging from 0 V to -0.2 V, the SEM image of memristor device array (e) and the single device (f). g, The vertical structure of the memristor by TEM observation, where the thickness of AlO_x is approximately 6 nm.
Fig. 3. Artificial intelligence-based analysis of DDV and CCV. a, Principal Component Analysis of DDV. b1, Schematic illustration of long short-term memory cell of cycle i and cycle i+1, where the physical parameter of cycle i (i ranges from 1 to 255) is extracted from IV curves like b2, including HRS current, current before Set, Set voltage, LRS current, Reset voltage/current and current/voltage after Reset. c-j, The distribution of the Set voltage, voltage after Reset, LRS current, current after Reset, Reset current, HRS current, current before Set, and Reset voltage for 256 cycles, where the grey dots indicate voltage values and the blue dots indicate current values. k-l. The SHAP value and the mean value of the SHAP of the contribution of all the physical parameters to the Set voltages.
Fig. 4. RTN analysis. a, Power spectral density. b1-b2, Capture and emission time and, c-e, the time lag plot of the three kinds of RTN signals, where the three kinds of RTN signals are under the V_BG 0 V, -0.1 V and -0.2 V, respectively. f1, Demonstration of the RTN signal and f2, the binarized strategy. g, Peripheral circuit of the memristor to extract the RTN signals or the set statics as entropy source (by using different load resistance or comparing voltages). h-j, Exhibitions of the binarized matrix of the binarized random numbers originated from the three kinds of RTN signals.
Fig. 5. Hamming Calculation and the cryptosystem. a, Hamming Weight. b, Intra-HD and c, Inter-HD of the CCV and DDV. d, The spatiotemporal variability including DDV, CCV and TTV as hardware primitive for random number generation. e-f, Illustration of a RSA-type cryptosystem, including key generation, message encryption and decryption, digital signature and authentication.

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