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The future is frozen: cryogenic CMOS for high-performance computing

Saligram R., Raychowdhury A., Datta Suman

Chip, 2024, 3(1): 100082-12. DOI: 10.1016/j.chip.2023.100082

Fig. 29. Cooling cost for various non-ideality factors and normalized power reduction obtained by supply voltage scaling across temperature.

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Fig. 1. Transistor transfer characteristics in linear and saturation regions for NMOS (a, b) and PMOS (c, d) showing linear increase in ON current, exponential decrease in subthreshold leakage current.
Fig. 2. Extracted subthreshold slope and threshold voltage in linear and saturation regimes for NMOS and PMOS across temperature.
Fig. 3. a, 3D structure depicting dipole engineering in MOSFET. b, Work function difference created by addition of dipole layer.
Fig. 4. Normalized increase in device ON current at nominal supply voltage across key temperature points.
Fig. 5. RO Simulation.
Fig. 6. Variation of I_ON and I_OFF under 3σ V_th variation with 2000 Monte Carlo samples of threshold voltage retargeted NMOS at 300 K and 77 K showing lower I_OFF spread at 300 K compared to 77 K and lower I_ON spread at higher V_DD.
Fig. 7. Variation in I_OFF across temperature for a given 3σ V_th variation showing the spread gets worse as temperature decreases.
Fig. 8. Variation (percentage change) in I_OFF from its nominal value across supply voltage for varying percentage changes in V_th at 300 K and 77 K showing stronger dependence on V_DD at higher ΔV_th at 77 K.
Fig. 9. Elmore delay distribution of top critical paths of a 64-bit Arm processor across technology nodes indicating the increasing contributions of interconnect creating performance bottlenecks.
Fig. 10. Normalized resistance of BEOL layers across temperature showing reduction at lower temperature.
Fig. 11. Extracted resistivities of BEOL metal layers and calibrated models which useFS-MS theory.
Fig. 12. Normalized cell delay improvement at cryogenic temperature averaged across the standard cell library showing ∼3x improvement compared to subsequent technology node.
Fig. 13. Normalized input pin capacitance across the iso-I_OFFtuned standard cell library for different drive strengths showing increased value at lower temperature due to higher charge accumulation for same gate overdrive voltage.
Fig. 14. Normalized input pin capacitance across the iso-I_OFF tuned standard cell library and corresponding targeted V_th for different temperature points.
Fig. 15. Performance benchmarking of Cortex-A53 core at nominal V_DD at different temperature points indicating percentage improvements. At 100 K, we can achieve the performance of a Class-A Core using the iso-I_OFF SC library.
Fig. 16. Improvements in physical design metrics viz., combinational gates, inverter/buffer counts, wire length, via count, cell and gate count, and total cell area at 100 K due to improvement in standard cell performance and reduction in interconnect resistance at cryogenic temperature.
Fig. 17. Normalized performance of 64 bit Arm Cortex-A53 across multiple supply voltages at different temperatures.
Fig. 18. Performance per watt versus performance of 64 bit Arm Cortex-A53 indicating up to 4x improvement at iso-frequency by scaling down the temperature from 300 K to 150 K and corresponding supply voltages from 0.6 V to 0.4 V and up to 3.7x by going from 300 K to 100 K and reducing supply voltage from 0.8 V to 0.4 V.
Fig. 19. Improvement in bulk thermal conductivity of substrate silicon at cryogenic temperature showing more than 10x increase (recreated from ref.¹⁹).
Fig. 20. Flow diagram for thermal analysis starting from design database, switching activity files and material thermal property files to obtain heat map of the chip.
Fig. 21. Thermal heat map for ARES core implement in 7
Fig. 22. Butterfly diagram for SRAM cells under V_th variation with 1000 Monte Carlo samples at a, 300 K, V_DD = 0.7 V, b, 77 K, V_DD = 0.7 V, c, 77 K V_DD = 0.2 V showing degradation in WC SNM. d, proposed iso-V_th solution at 77 K, V_DD = 0.3 V, compared with e, iso-I_OFF at 77 K, V_DD = 0.3 V and f, iso-V_th V_DD = 0.7 V for scalability.
Fig. 23. Supply voltage reduction for different scenarios - iso μ/V_DD for hold, iso- μ/V_DD for read and iso- μ/V_DD for write. The devices are V_th tuned at 77 K.
Fig. 24. Retention probability of failure versus retention time for 28 nm 2T EDRAM shows 3σ mean time increases by > six orders of magnitude due to ultra-low leakage at cryogenic temperature.
Fig. 25. Array power vs bandwidth for different temperatures and refresh power/read write energies across temperature for 1 kb 2T gain cell EDRAM array in 28 nm bulk CMOS.
Fig. 26. Operation principle of FBRAM—the presence or absence of charge carriers in the body modulates the V_th of the device and consequently the ON current.
Fig. 27. ΔI_READ at 77 K with Si FBRAM showing two retention states and SiGe FBRAM showing four retention states.
Fig. 28. Cache miss per 1000 instructions at 77 K at iso-silicon footprint showing 38%, 57%, and 66% reduction for 2T EDRAM, 1bit/cell FBRAM and 2 bit/cell FBRAM compared to 6T SRAM.

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