INTRODUCTION
With the increase of computing power and mobile communication speeds in recent years, Internet of Things (IoT) has become much more important than ever before1. IoT could realize not only big data accesses collected by the sensor nodes, but also real-time computer controls of objects ranging from small devices to vehicles or factories (see Fig. 1 for the conception). Since the introduction of 5G high-speed wireless communication in 2020s, the possibilities of IoT have been considerably expanded2. A data transfer rate of approximately 10-20 Gbps is expected, which is essential for new applications such as automatic driving3, tele-working4, extended reality (XR) (including virtual reality (VR), augmented reality (AR) and mixed reality (MR)). These real-time high-speed communications form the new smart-city lifestyles5. The advanced mobile communication of 6G is expected to appear in the 2030s6, with its applications expected to be significantly expanded.
Fig. 1. Concept of IoT network with integrated LSI chips. |
These services are provided by the complementary metal-oxide-semiconductor (CMOS) large-scale-integration (LSI) chips, which are interconnected by wireless radio communications. LSI chips can integrate several types of components in a single device, such as computing circuits, wireless communication devices and energy harvesters. Integration of these components into one chip enables standalone operation, which means the computing nodes can be placed anywhere as far as the chip could operate, which thereby significantly expands the possibilities of data processing.
Analog LSI designs must understand both device physics and circuit phenomena. There are several restrictions for device designs, especially for fully integrated devices, since the standard CMOS processes specialize in designing transistors (or diodes and passive elements), rather than other semiconductor devices. However, these devices will expand the possibilities of analog LSI chips by adding applications and functions such as energy harvesting, sensing and wireless communication. For circuit topologies, in order to drive the devices, it will be necessary for the corresponding circuits to realize new applications and functions such as charge pumps, maximum power point tracking, and back-scattering. The components on standalone LSI chips diverse from the power sources by the energy harvesting, power regulators, application units and data transferring, as shown in Fig. 2. Every component is needed to be understood by standalone LSI chip designs, including the unique physics (for device levels) and topologies (for circuit levels) that make it difficult to design the entire system.
Fig. 2. General standalone LSI chip components. |
This article reviews the current technologies for standalone LSI chips aimed at IoT applications. The article is composed of energy harvesters (Section 2), control units (Section 3), application blocks (Section 4), data transfers (Section 5), as well as examples and future styles (Section 6). On-chip device designs were discussed in Sections 2 and 4, the circuit topologies and phenomena were described in Sections 3 and 5, and the operation of the LSI chips was explained in Section 6.
ENERGY HARVESTERS
Energy harvesting is the power source component of the standalone system to drive LSIs, enabling it to be placed anywhere to collect energy from the environment. There are several energy harvesting methods, and making the correct choice is critical to ensuring the maximum performance of the devices7.
Optical method
Optical energy harvesting generally utilizes sunlight and is the most commonly used energy source. It is featured several advantages: 1) sunlight is accessible to almost the entire world 2) sunlight exhibits the largest energy of approximately 1 kW/m2 2 compared to other sources, 3) optical energy harvesting can be performed by simply placing photovoltaic (PV) cells, which are essentially pn diodes8. The main drawbacks of optical energy harvesting are: 1) energy isn't available when the environment is dark or at the night time, or it will be shaded by any obstacles and 2) the climate change contributes to the large power supply fluctuation.
Designing PV cells requires an understanding of fundamental optical theories. The light absorption to the material is expressed as:
α=4πkλ,
where, α is the light absorption coefficient, k is the imaginary part of complex refractive index, and λ is the wavelength. The well-known light absorption characteristics of silicon have been reported by Green9.According to the expression, shorter wavelengths are absorbed at the illuminated surface region while longer wavelengths travel deeper.
Fig. 3 illustrates the basic type of an on-chip PV cell with operation modes. A critical issue for on-chip PV cells is the unavailability of front texturing, which is the basic technique for minimizing surface light reflectance10. Texturing needs an etching process; therefore, it is expected to be challenging to form texturing to on-chip PV cells even with post-processing due to the fact that it will affect the other areas of LSI chips. Furthermore, it should be noted that both p- and n-regions are concentrated on the front surface, which is contrary to the general solar cell devices where p- and n-regions are separated on each front or bottom surface (although there are exceptions). Device designers should understand that on-chip PV cells are essentially reversed interdigitated back contact (IBC)’ structures11.
Fig. 3. Fundamental on-chip optical device conception. |
On-chip PV cells available on standard CMOS process for driving circuits was proposed by Arima et al. in 200612. The proposed device connected two pn-junctions of p-substrate/n+ and p+/NWell in series to obtain a high voltage with the conversion efficiency of 2.6% and the output voltage of 0.6 to 0.83 V. A single silicon PV cell outputs approximately 0.4 to 0.6 V (dependent on illumination), and a series connection enhances the output voltage without charge pumps. Furthermore, the adoption of silicon-on-insulator (SOI) process for a large series-connection of PV cells was reported by Bellew et al.13. The SOI process was adopted for micro-electro-mechanical-systems (MEMS) applications and could connect the maximum of 200 PV cells, with the open-circuit voltage reaching up to 88.5 V with 8.3% conversion efficiency. From these reports, it can be seen that when connected in series, each PV cell will output approximately 0.4 V and, therefore, multiple PV cell connections or charge pumps will be essential for driving circuits.
Standard CMOS processes enable the formation of multiple pn-junctions along the depth direction using the triple-well process. Horiguchi proposed an element-separated on-chip PV cell by using triple-well CMOS process14. The light-induced carriers can affect the subthreshold voltage of the transistor and make its operations unstable; triple-well layer works as a barrier against these carriers. Here, the triple-well process results in the formation of multiple pn-junctions along the vertical direction; therefore, a few designs will cut off all carriers generated at the substrate and the large efficiency drops. Steffan et. al. reported the structural designs, including the shape and layer designs of on-chip PV cells15. When only surface-generated carriers were collected, only less than 10% output power was available from the full region scheme. When applying the surface passivation, the output power could be enhanced by approximately 10%, and the patch shape was better than the bar shape. The performances were also influenced by the surface design from both the electrical (passivation) and optical (anti-reflection) aspects. Enhancing the conversion efficiency by forming an anti-reflection (AR) coating at the front-side was also reported16. Two types of AR coats (Al only and Al/Mg stack) were evaluated, and the performances were significantly enhanced by forming an Al/Mg layer stack as an AR coating, and the conversion efficiency reached as high as 12.8%. For standard CMOS processes, light illumination is not estimated, and AR coat forming will need post-processing. Hung et al. proposed a contact-shading-free PV cell by adopting the reversed LSI chips17. Electrical contacts were the sources of potential power loss for PV cells by shading illuminations, and the general CMOS processes formed all the contacts at the front-surface; therefore, shading loss could be avoided by reversing the LSI chips. The reversed light absorption properties should be taken into careful consieration for this type of cell : the shorter wavelength will be absorbed at the bottom surface (near the illuminated surface), and the longer wavelength light will reach the pn-junction. The reported cell efficiency is still limited to 4.6%, and further improvement is highly desired.
The proposed on-chip PV cell in the current work utilized the gate active region at the shrunk CMOS processes18. This proposed cell utilizes carrier tunneling at thin oxide, generally known as tunnel oxide passivated contact (TOPCon) in PV fields19. For on-chip designs, the gate region of poly-Si(n++)/thin oxide/substrate(n−) can work as TOPCon contacts, which improves cell performance by reducing the contact losses. Another on-chip PV cell adopts the double-ring shaded-contacts formed outside the light aperture window and eliminate the contact-shading loss, which contributes to the best performances among the existing on-chip PV cells20.
A few study reports on image sensing use wavelength-dependent light absorption characteristics. Park et al. proposed the use of simultaneous image sensing and PV energy harvesting adoptingg two depth-directed diodes in series (shallow diode as the image sensor and deep diode as the energy harvester)21.
The above mentioned cells still exhibit less cell efficiency when compared with silicon solar cells fabricated by dedicated processes that feature higher than 20% cell efficiencies for mass-production8., 22.. A chip-size silicon solar cell with an efficiency of 18% (under 250 sun of high concentrated illumination) has also been reported23, implying that potentially much higher cell efficiencies are possible for on-chip devices. A theoretical cell efficiency of approximately 21% was predicted by Shewchun et al. in 1976 for MOS (MIS) structures24.
The performances of representative on-chip (or reproduced) PV cells are listed in Table 1. Although comparisons are difficult to be conducted due to the difference in illumination, the cell efficiency will be the most intriguing index for readers. The output voltage can be enhanced by adding series-connections; however, this increases the cell area, so the adoption of a charge pump might be a better option. Unlike other transistor components, on-chip PV cells are less dependent on CMOS-process scale for their performances. Performances are determined based on device designs by forming diffusion layers, wells and contacts.
Table 1. Cell performance comparisons of on-chip photovoltaic cell devices. |
| Name | Process | Area | Illumination | Efficiency | Output voltage | Number of series connections |
|---|---|---|---|---|---|---|
| Mulligan et al.23 (Reference) | N/A (Not on-chip) | 5.29 mm2 | 250 sun | 18.4% | 813 mV (VOC) | 1 |
| Arima et al.12 | CMOS 0.35 µm | 6.1 mm2 | 2,000 lux | 2.6% | 0.6 to 0.83 V | 2 |
| Horiguchi14 | CMOS 0.18 µm | 1.38 to 2.06 mm2 | 1,000 to 31,000 lux | Unknown | 0.9 to 1.3 V | 2 to 3 |
| Hung et al.17 | CMOS 0.35 µm | 1.5 mm2 | 21 mW (980 nm) | 4.6% | 0.5 V | 1 |
| Watanabe et al.16 | CMOS reproduced | 0.0025 to 0.015 mm2 | 650 cd | 12.8% | 0.25 V | 1 |
| Bellew et al.13 | CMOS-SOI NMOS-SOI (Unknown node) | 0.16 mm2 (single cell) | AM1.71 or AM2.0 | 7.5 to 11.7% | 8.4 to 88.5 V (VOC) | 20 to 200 |
Thermal method
Thermal energy harvesting is known as another way of energy harvesting alongside optical energy harvesting25. It is featured the advantage of wide availability of energy harvesting since the temperature gradient appears for the entire area. However, to obtain energy effectively, one needs ingenuity, and several types of methods have been considered for the same.
The most common method is to use thermoelectric generators (TEGs) to collect thermal energy from the surroundings. Fig. 4 illustrates the fundamental operation of a TEG. A TEG is comprised of separated p- and n-type semiconductors connected by metals at different temperatures. The fundamental mechanism is the Seebeck effect; a temperature gradient is generated by the different temperature responses of p- and n-type semiconductors, and the Peltier current is obtained as the harvested energy. Generally, n-type materials exhibit a high Seebeck coefficient as the electron is of larger carrier mobility than the hole in p-type materials’ carrier, and the heat escapes easily (although the final Seebeck coefficient is also dependent on doping concentration). Strasser et al. proposed a micro-scale TEG (µ-TEG) unit that was compatible with standard CMOS processes26. The proposed µ-TEG adopted pure poly-Si and poly-Si0.7Ge as the thermoelectric materials, and fabricated at surface as the µ-TEG using micromachining processes to form legs structure. The results showed that the adoption of pure poly-Si in µ-TEG exhibits higher output power and is much more beneficial for energy harvesting. In 2015, Cornett et al. proposed a chip-scaled TEG using Bi2Te3 as the TEGs27. Bi2Te3 is a highly effective thermoelectric material, and applying it in TEGs has a huge potential in enhancing the output power28. Approximately 4 to 5 times the output voltage could be obtained by forming TEG structures in the quasi-lateral direction (by mesa structures), which expressed the effectiveness of Bi2Te3 materials as TEGs.
Fig. 4. Fundamental thermoelectric generator (TEG) conception. |
There have been reports demonstrating that electric polarization (similar to piezoelectricity) has been used to generate power. Cuadras et al. proposed a thermal energy harvester using pyroelectric cells29. A pyroelectric cell device is comprised of two piezoelectric materials of screen-printed lead zirconate titanate (PZT) and polyvinylidene fluoride (PVDF). It exhibits electric polarization against temperature and can be used for thermal energy harvesting. A full-wave rectifier circuit composed of four bridge diodes is adopted to store the generated carriers, which is also utilized in piezoelectric energy harvesting. In conclusion, this type of thermal energy harvesting is derived from piezoelectric energy harvesting.
Piezoelectric method
A piezoelectric device could convert mechanical pressure into voltage30. Electric polarization occurs when mechanical stress is applied to the material, and this effect is widely used for the operation of transistors in high-electron-mobility transistor (HEMT) of GaN/AlGaN hetero-junction devices to form 2D electron gas (2DEG)31 for energy harvesting. The advantage of piezoelectric devices lies in the fact that power can be generated whenever stress is applied to the material. The drawback is the lack of material options, quartz or some ceramics are required to obtain sufficient power. Since crystalline silicon does not exhibit piezoelectric effect, the formation of a piezoelectric energy harvester requires some post-processesing for standalone LSIs. There are several candidates for the choice of piezoelectric materials, such as SiO2 (quartz)32, BaTiO3 (nano films)33, ZnO (nano structure)34, HfO2 (thin film)35 and Li-compounds (LiTaO3 or LiNbO3 crystals)36. Designers should choose the appropriate material by taking cost (some materials include rare-metals) and integrability into consideration.
Piezoelectric energy harvesting is equivalently expressed as two states: the series of passive elements connected to the current source and connected by the trans to output electrical power at the non-resonance state, and the parallel capacitor and resistor connected to the current source with direct electrical output at the resonance state30. Resonance-state is when the series RLC shows resonance, ωL=1ωC, and the effects of both L and C disappear in the electrical circuit. A high voltage can be obtained at this state, and this resonance is aggressively utilized. The power sources of piezoelectric harvesters are acoustic sounds, footsteps37, and other mechanical elements, and the difference in the power sources will determine the suitable piezoelectric harvester mode of resonance and non-resonance. Pyun et al. evaluated the performance differences of piezoelectric acoustic absorbers between resonance and non-resonance methods. The resonance method exhibited high sensitivity around the resonance frequency even when the bandwidth was strictly restricted. Furthermore, the non-resonance method exhibited a better frequency response and required high transmit voltage38. Lin et al. reported the resonant characteristics for piezoelectric energy harvesting by combining theoretical resonant analysis with measurements of experimental voltage and power. They concluded that high voltage gain at the resonant frequency points could be achieved by the resonance method39. These results imply that the resonance method could provide high performance for restricted bandwidth applications; therefore, acoustic energy harvesters will be suitable for the resonance method due to the fact that the frequencies can be predicted to a certain extent. Tang et al. summarized the characteristics of piezoelectric harvester modes, including the existence of contacts. For most non-resonance type, the main drawback is the large size of the system and unsuitability for wearable and IoT applications (only restricted to the installation types).
The advances in this field are achieved by expanding the bandwidth for the resonance method and enhancing the conversion efficiency. Tan et al.40 improved the broadband piezoelectric energy harvesting frequency. The hybrid energy harvester exhibits a base excitation for narrow bandwidth and galloping vibration for low natural frequency that are unique for structures41. The combination of the two methods of base excitation and galloping vibration will contribute to the expansion of the bandwidth. Kushino et al. proposed a full-bridge-energy-harvesting (FBEH) circuit aimed at increased conversion efficiency and higher maximum power point voltage42. The proposed circuit operates with three states with the utilization of two diodes between the energy harvester and output electrical block for phase-regulations, and the switched inductor at the energy harvester block contributes to the peak output voltage. Wenck et al. proposed the AC power supply circuits from piezoelectric energy harvesting. As the majority of the energy harvesters generate DC power supply, AC power supply from energy harvesting can be useful in some situations. The mechanical vibration is suitable for AC power supply as it has the frequency, and the proposed circuit generated x00 Hz AC power supply. Here, the result was obtained under the cryogenic condition of 135 K since the high temperature (even room temperature) causes noise, and thermal noise eliminates the AC power as the harvested power is generally small. Harerimana et al. proposed a mechanical energy harvesting circuit with an extremely small power of 10 nW43. The authors compared five circuit topologies by numerical simulations, concluding that the topology comprised of two transistors with two storage capacitors was the optimal among them with the efficiency of 50% at MPP.
Hybrid method
The hybrid method is applied to a few situations. The pyroelectric cell proposed by Cuadras et al.29 is also categorized as a hybrid method. Wahbah et al. proposed a thermal and vibration hybrid energy harvesting method aimed at wearable device applications44. The system drew energy from the device-wearing human activities (piezoelectric) and body temperature (thermal). The obtained power densities were 2.2 µW/cm2 from the TEG and 7.4 µW/cm3 from the piezoelectric energy harvester. Here, it should be noted that the TEG is the plate and the piezoelectric energy harvester is three-dimensional.
Thermal energy harvesting is often combined with radio frequency (RF) energy harvesting45., 46.. The common advantage is the wide availability of thermal and RF energies, and combining them into one device is effective in enhancing the obtained powers.
Summary
Fig. 5 illustrates the equivalent circuits of the representative energy harvesters. Each equivalent circuit shows the characteristics of energy harvesting: diode-operational, frequency-dependent or DC-powered. As explained before, the piezoelectric energy harvester can output AC power supply and has the potential for unique applications.
Fig. 5. Equivalent circuits of the energy harvesters. |
The importance of energy harvesting depends on the packaging of the chips. The optical energy harvester needs light aperture as the illumination window; therefore, there is an issue with chip packaging. Additionally, the carrier generation can negatively affect the transistors, causing them to malfunction. Therefore, barriers surrounding the transistors, such as the triple-well structure or the oxide passivation layer, are required. For the thermal energy harvester, a temperature gradient is essential and the thermal conductivity of the packaging must be taken into consideration (thermal insulation materials are unsuitable). High acoustic-transmission materials are required by the piezoelectric energy harvester, and the packaging design is also important47. To summarize, energy harvesters draw the energy from the outside, and interconnection between the chip-internal and outside occurs, and the packaging is capable of addressing this issue.
CONTROL UNITS
Control units consist of the clock generators as well as power controllers of the charge pumps and the maximum power point tracking circuits.
Clock generation
General computers generate clocks from quartz oscillations by utilizing the piezoelectric effect48. In 1999, Nguyen et al. proposed a CMOS-integrated quartz resonator with high Q-factor49. The main advantage of a quartz clock generator is the stability of generated frequency; however, MEMS processes are needed for integration and a relatively high voltage (and large power consumption) required for driving, and hence, the quartz clock generator may be unsuitable for IoT applications.
The simplest clock generator is realized by a ring-oscillator (RO) and odd stage cascaded inverters. Cañada et al. proposed a small leakage ring-oscillator mentioned as 'dynamic leakage suppression (DLS) ring oscillator’ (DLSRO)50. DLSRO composes each inverter stage using four complementary top and bottom transistors as the output is connected to the gates of PMOS (VDD-side pull-up logic) and NMOS (VSS-side pull-down logic), and they work to insulate VDD and VSS. Therefore, VDD or VSS momentarily supplies the voltage to the inverter block.
Another method is to utilize the RC or LC resonance circuits for clock generation. Barrow et al. proposed a small area RLC-series resonance oscillator for middle frequency clock generation51. The proposed circuit regulated the resonator by sandwiching the tuning electrodes, formed the resonator by MEMS-processes, and drastically reduced the device area by avoiding the use of passive elements. Hwang et al. proposed a programmable RC-LC hybrid oscillator which generated sub-GHz clock designed on CMOS processes52. The RC block worked as a fixed-frequency source that provided power to the LC block for generating high-frequency clocks. Here, the LC output was fed back to the RC oscillator and controlled the capacitor charge, thus enabling the generation of programmable clock.
The RO and LCO hybrid on-chip clock generator was proposed by Kellis et al53. The RO block was employed as the reference clock for internal digital processing, and LC block generated a more stable and accurate clock that was used for information transferring. Compared with quartz clock generator, the proposed circuits exhibited considerably smaller power consumption and shorter interrupt times, as the RO and LCO blocks featured faster startup and stop characteristics and smaller power losses.
The fundamental clock generation circuits are illustrated in Fig. 6. Table 2 summarizes the representative clock generator performances. As the RO exhibits very small power consumption, the RO-based system can be used in low-power devices. However, it is difficult for RO to output stable clocks on its own, and combination with RLC-series resonance circuit can improve the clock accuracy. The choice of the circuit will depend on the accuracy level of the clock, and accurate clock generators are required for wireless communication and other applications.
Fig. 6. Fundamental clock generation circuits. |
Table 2. Performance comparison of the representative clock generators. |
| Name | Process | Topology | Frequency | Area | Power consumption |
|---|---|---|---|---|---|
| Cañada et al.50 | CMOS 0.18 µm | Ring-Oscillator | 0.1 to 1,000 Hz | 0.00152 mm2 | 60 pW |
| Barrow et al.51 | CMOS-MEMS 0.35 µm | Pseudo-RLC | 32.768 kHz | 0.0154 mm2 | 2.1 µW |
| Hwang et al.52 | CMOS 14 nm | RC-LC hybrid | 1 - 100 MHz | 0.12 mm2 | 50.4 mW |
| Kellis et al.53 | CMOS 0.18 µm | RO-LC hybrid | 100 MHz | 0.25 mm2 | 10.4 mW |
Maximum power point tracking
Energy harvesters need to control output power so as to obtain the maximum power, and generally, the maximum power point tracking (MPPT) method is used. For PV cells, MPPT should track the light illumination intensity because the MPP depends on photocurrents, which is especially important for indoor applications. Chang et al. proposed a time-based MPPT for on-chip PV cells for indoor applications. The time-based MPPT (TBMPPT) unit regulated the entire system of PV cell output, three switched-capacitor DC-DC converters (SCDCs), and a digitally controlled oscillator (DCO). TBMPPT was adopted to reduce power consumption, a 4-bit signal was treated as the input signal to the DCO for controlling the switching frequency, and a 2-bit signal was used for SCDCs to select one of three capacitors and adjust the frequency for high-efficiency. Ferro et al. proposed a PV power control method by driving both DC-DC converter and MPPT unit from a common PV cell54. The proposed system utilized multiple-level detectors for MPPT unit and control circuit block, and the combination of it with auxiliary oscillator and DC-DC converter units enabled cold startup. Kim et al. proposed a wireless sensor-oriented PV MPPT circuit with a significantly high efficiency of 99.6%55. They introduced a successive approximation register (SAR) and a counter (CNT) which was aimed to be compatible with the fast transient response and small steady-state oscillation. The MPPT algorithm consisted of two modes of SAR and CNT; the SAR mode was used to adjust the duty-ratio for fast transient response and low power consumption for tracking the MPP, while the CNT mode used at stable illumination conditions.
Cao et al. proposed an MPPT unit for thermoelectric energy harvesting56. The proposed circuit aimed at treating bipolar-voltages as the TEG output was bipolar of p- and n-type semiconductors, and enabled cold-startup from the low voltage of TEG by designing boost/flyback hybrid converter (BFHC) composed of nine transistors to supply VDD, VOUT, and VSUP that are used to control the system. The circuit could start up from ±25 mV with a high efficiency of 84%.
Dayal et al. proposed a non-MPPT output control system by controlling the duty cycle of mixed-signal components for achieving the maximum power, which reduced area and avoided the complex layout of the block57. The proposed circuit was designed on discrete elements and designed for electromagnetic energy harvesting. The output of power converter was connected to a delay block, and a comparison of the previous state enabled the regulation of duty cycle.
The performance comparison of different MPPT units is summarized in Table 3. The MPPT units depend on the energy harvesting sources, hence, different circuit topologies will be necessary for integrations.
Table 3. Performance comparison of the representative MPPT units. |
| Name | Process | Power source | Area | Efficiency |
|---|---|---|---|---|
| Chang et al. | CMOS 0.18 µm | Photovoltaic | 1.454 mm2 | 68.3% |
| Ferro et al.54 | CMOS 0.18 µm | Photovoltaic | 1.575 mm2 | 57% |
| Kim et al.55 | CMOS 0.35 µm | Photovoltaic | 3.15 mm2 (the external inductor excluded) | 99.6% |
| Cao et al.56 | CMOS 0.18 µm | Thermoelectric | 1.625 mm2 | 84% |
| Dayal et al.57 | Discrete | Electromagnetic | N/A | 77% |
Charge pump
It is necessary to enhance the voltages obtained from energy harvesters, which are in the range of several tens to hundreds of mV. Since circuit operation requires a voltage of 1V or higher, charge pump block is widely used in standalone devices.
One of the most common topologies was proposed by Dickson in 1976, which is known as Dickson charge pump. Dickson charge pump utilized diode-connected series NMOS transistors with internal capacitors and had two phases for voltage boost. By boosting multiple stages, an output voltage of approximately 40 V was demonstrated by the circuit. Another well-known topology is the cross-coupled charge pump (CCCP) proposed by Favrat et al. in 199858. The circuit was based on a cross-connected NMOS-only charge pump cell proposed for DRAM that was featured with high-speed and natural reverse bias of junctions59. In addition, solving voltage drops caused by NMOS transistors with PMOS biasing60 was included in CCCP to eliminate the parasitic elements of bipolar transistors for enhancing the efficiency. Two designs of integrated or external capacitor connections were evaluated with different efficiencies. The following charge pumps are based on these two topologies.
A few charge pumps aim to solve the unique issues. Jung et al. proposed a self-oscillating charge pump that enabled cold-starting even under minimal light illumination with a minimum cell output voltage of 0.14 V PV to a maximum of 5.2 V61. The proposed circuit integrated the charge pump into an RO, and compatible voltage doubler and clock generator have been designed. Therefore, it could cause cold-startup under light illumination. Rumberg et al. proposed a charge pump topology for floating-gate transistor operation62. Floating-gate transistors are widely used in flash memory devices64, and this circuit topology could provide up to 16 V of high voltage from 2.5 V supply voltage. The use of a long gate of 0.35 µm is considered to contribute to a high voltage boost. Ballo et al. proposed a 50 mV cold start charge pump block at the theoretical design level63. The circuit was based on a cross-coupled scheme with internal resistances that work as rectifiers, enabling it to start from a small voltage.
Enhanced charge pump performances have been achieved by enhancing the conversion efficiency, operation frequency, or by reducing the area. Pelliconi et al. enhanced the available frequency of CCCP to 100 MHz of high frequency by using low-voltage transistors65. Jiang et al. proposed a high-efficiency charge pump that regulated the charge transfer strictly to cut undesired transfer66. Shih et al. proposed an inductor-less charge pump for small areas with a band-gap reference block for regulation67. Lee et al. proposed a 1GHz operational charge pump with the adoption of Schottky barrier diodes (SBDs)68. Although the proposed circuit was not on-chip integrated, the adoption of SBDs for regulations enhanced the operational frequency to 1 GHz, which is what is desired in RF applications. There have been reports on on-chip integrated SBDs using NWell/metal Schottky interfaces69., 70., and the combination of the reported circuit with on-chip SBDs will contribute to the realization of LSI integrations.
The important charge pump topologies with their representative performances are listed in Table 4. Some topologies are featured with their own advantages and are strongly optimized for unique situations. Charge pump topologies suitable for their use should be selected by circuit designers.
Table 4. Performance comparison of the representative charge pump topologies. |
| Name | Process | Frequency | Area | Input | Output | Efficiency |
|---|---|---|---|---|---|---|
| Dickson | NMOS (Unknown node) | 1 MHz | 0.144 mm2 | -12 to +5 V | 39.1 V | Unknown |
| Favrat et al.58 | CMOS 2 µm (external capacitor) CMOS 0.7 µm (integrated capacitor) | 0.1 to 10 MHz | 0.784 mm2(2 µm) 0.15 mm (0.7 µm) | 1.1 V | 3 V (2 µm) 6 V (0.7 µm) | 95.6 (2 µm) 80 (0.7 µm) |
| Jung et al.61 | CMOS 0.18 µm | Self-generation | 0.86 mm2 | 0.14 to 0.5 V | 2.2 to 5.2 V | 50% |
| Rumberg et al.62 | CMOS 0.35 µm | 1 to 20 MHz | 0.069 mm2 | 2.5 V | 16 V | 34% |
| Lee et al.68 | Off-chips | 1 GHz | N/A | 0.2 V | 1.3 V | Unknown |
| Ballo et al.63 | FD-SOI 28 nm (Theoretical) | 1 MHz | 0.0116 mm2 | 50 mV | 270 mV | 80% |
APPLICATIONS
Sensors
Sensing is the most featured application of standalone LSI chips utilized for big data collections and remote controls. The range is diverse from optical, mechanical and temperature of the environment to chip yields and safe-operations.
Optical sensing
Optical sensing is similar to optical energy harvesting, the only difference between them is whether the light is used as the energy source or for information. However, energy harvesting must implement the MPPT unit to achieve the maximum power; on the contrary, the optical sensor simply needs the device itself (and the surrounding circuit) and so the component is much simpler.
The simplest device is the photodiode, which is a single pn-junction under reverse-biased operation and used for measuring photocurrent. Here, the obtained photocurrent is converted to voltage and needs the conversion circuit71. There is an algorithm that uses zero-modes (zero-voltage or zero-current) to separate the DC and AC parts of the system for optical signal sensing72. Our proposed approach applied the zero-current mode that used VOC of the on-chip PV cell and was used to detect the light intensity73. Since the proposed system utilized the voltage signal directly, the removal of current-voltage converters is enabled. This feature reduced the area and power consumption while maintaining the sensitivity.
Our works introduced the methods to detect RGB, UV (ultraviolet), and infrared (Ir) colors by combining multiple-pn diodes with current rectifiers (on LSI chips, they are easily fabricated by pn-diodes)74., 75.. The proposed methods didn't need any color filters that were required by the previous works for good color detection76., 77., and current rectifiers enabled the removal of color filters and corresponding post-processing. The device structure is available for triple-well CMOS processes. Fig. 7 illustrates the light responses of vertical multiple pn-junctions available in triple-well CMOS processes. A maximum of three series pn-junctions can be formed, and shorter wavelength light is absorbed at the near-surface region; therefore, different light responses can be detected from each diode to realize color sensing.
Fig. 7. Vertical multiple pn-junctions as separated light responses (contacts are omitted). |
Another optical sensing method utilizes a phototransistor, which is designed based on SiGe-BiCMOS technology (also mentioned as SiGe-Heterojunction-Bipolar-Transistor (HBT)). The use of SiGe-BiCMOS technology enhances the sensitivity of photodiodes for larger light absorption in SiGe compared with silicon78, and this property works well to cover the lower sensitivities of on-chip photodiodes. Additionally, the band-gap energy of SiGe (0.7 to 1.1 eV) is smaller than that of silicon (1.1 eV), and controlling the mole fraction of Ge enables to adjust the band-gap energy of the material, thereby controlling the optical responses79.
For optical sensing, high sensitivity and wide coverage of wavelength are the critical factors. Optical sensing is strictly affected by the material characteristics as the band-gap energy determines the available wavelength range (shallower band-gap energy will respond to longer wavelength of Ir light). Ajiki et al. proposed an Ir photodetector designed using n-type silicon that formed the organic nano-dot arrays at the top of the substrate80. Organic semiconductors such as 3, 4, 9, 10-perylene-tetracarboxylic-dianhydride (PTCDA) and copper phthalocyanine (CuPc) have been adopted as the nano-dot array materials, and a band gap energy of approximately 0.4-0.43 eV was obtained, which could activate the Ir light. Zhao et al. proposed a molybdenum(IV) sulfide (MoS2) photodetector formed on sapphire substrate81. The main feature of MoS2 is its tunable band gap energy, and available range can be diverse, ranging from THz electromagnetic wave to UV light82. Here, the band gap energy of silicon is 1.1 eV (at room temperature) and near-infrared (NIR) is the lower limit of the wavelength (approximately 1 µm). The utilization of a narrower band gap material such as Ge, SiGe, or MoS2 will expand the limit to cover longer wavelength light, and integration such as SiGe-BiCMOS process is the method used.
Mechanical sensing
There is a piezoresistive effect caused by the response to mechanical stress83, in addition to the piezoelectric effect that generates internal voltage. The resistivity (or mobility) changes under stressed situations, and its theoretical expression is as follows：(2)ΔΔRR0=πlσl+πtσt,where π and σ are the piezoresistive coefficient and stress, respectively, with the orientations as longitudinal (parallel to the current-flow) and transverse (normal to the current-flow). This phenomenon forms the fundamental theory of stress sensing and is featured with the following advantages: 1) the resistance change is proportional to the magnitude of applied stress, and 2) the resistance change is larger compared with other methods. Since the πs are anisotropic parameters, the crystal orientation determines the sensitivity of sensors. In addition to the stress sensor, it is also utilized to enhance MOS performances, known as strained-silicon devices84.
A piezoresistive pressure sensor is essentially a unipolar doped single silicon-layer. We proposed a fully integrated on-chip piezoresistive pressure sensor that operates at high-temperature environments85. The proposed device was featured with multiple pn-junctions between the surface-located sensor and the bulk, and current leakage was strongly suppressed by the internal pn-diodes. Another method to reduce leakage currents utilizes SOI substrate, which enables its operation till 300 ℃86. Besides the resistor-based design, piezoresistive CMOS sensors have been proposed by Baumann et al.87. Piezoresistive CMOS sensor forms the ring n- or p-doping regions at p- or n-regions (reverse to ring-doping) to set the current flow toward the depth direction (parallel to shear orientation) for detection of the shear stresses. The (100) wafer was used to eliminate the normal piezoresistive effects. Fig. 8 illustrates the concept of an on-chip piezoresistive mechanical sensor. The combination of two types of sensors will enable the detection of all of the three directed mechanical stresses to ensure the mechanical reliabilities of the system.
Fig. 8. Concept of on-chip piezoresistive mechanical sensors. |
When integrated, a Wheatstone bridge circuit is used to detect the resistance change of the sensor. Several Wheatstone bridge circuits have been reported regarding the elimination of capacitive noise88, integration process to a chip89, or enhanced linearity by using an asymmetric Wheatstone bridge90. The important factors required to be considered are low power consumption and high accuracy of the circuit.
Most piezoresistive sensor fabrications need CMOS-MEMS processes; therefore, fabrication costs will be higher than those of CMOS-only devices. Therefore, research on CMOS-process compliant piezoresistive devices is going on. CMOS-MEMS compatible processes have been researched using in-mold decoration (IMD) process91.
Temperature sensing
Temperature sensing is also an important application for environments of human activities and the reliabilities of facilities.
The Seebeck effect is used for temperature sensing, and on-chip Seebeck-driven temperature sensing was proposed by Zhou et al.92. The device was formed on n-type silicon, in which a Fe-Ga alloy worked as the Seebeck material. For LSI integration, the post-processing would support fabrications, and the sensitivity was higher than 40 µV/K. Furthermore, an organic semiconductor Seebeck device was proposed by Warwick et al., which was formed on a glass substrate93. Seebeck effect has been known as the fundamental theory regarding the temperature of the materials, however, its application to on-chip devices is still under research.
A transistor-based circuit was proposed by He et al.94 The circuit adopted the transistor’s threshold voltage as the index and is comprised of five transistors operated in the saturation region. The current-mirroring enabled the comparison of the threshold voltages of the cascaded transistors with the magnitude, and measurements in the range of - 20 to 100 ℃ were demonstrated. Here, the saturated currents included the channel-length modulation effect, and shrunk processes may not be suitable (the work uses 0.18 µm CMOS process). Later, the system-level design of on-chip temperature sensing was demonstrated95, which is featured with low power-consumption of approximately 1 µW with full-spec sensing activities of - 20 to 100 ℃.
Pathrose et al. proposed a temperature sensor using the temperature dependency of the band-gap energy of silicon96. This system utilized the difference in band-gap temperature dependencies between two diodes, in which these diodes are bipolar transistors. A complementary to absolute temperature (CTAT) characteristic to voltage was obtained by biasing two diodes with different current densities. The system was designed on SOI-CMOS process to reduce the leakage currents between the two diodes, and sensing from 25 ℃ to 225 ℃ was demonstrated, which would be suitable for oil drilling.
Another style of the temperature sensor utilized the piezoresistive effect, transducing the thermal-mechanical stress to the voltage97. Thermal expansion (or shrink) stresses of cantilevers were measured by the piezoresistive effect to monitor the ambient temperature.
Reliability sensing
Sensors include not only environmental measuring but also the reliabilities or securities that are related to manufacturing or operations.
An et al. proposed a process validation detector using RO topology98. The circuit detected the process corner that affected transistor performances, and its topology included the ratioed stage, composed of single-type MOSFETs with diode-connected load transistors. This circuit will help improve the reliability of LSI systems especially fabricated by unsophisticated processes.
Wang et al. proposed a safe-operation monitoring system for chips99. The system monitors PMOS transistor’s Vth, which was sensitive to damages such as negative bias temperature instability (NBTI) or hot carrier injection (HCI) during operation. Its accuracy was reasonably high as far as the devices were used under standard conditions, not under extreme conditions.
Anik et al. proposed an on-chip digital voltage and temperature sensor aimed at providing security and reliability100. The proposed sensor was comprised of multiple cascaded buffers with inserted D flip-flops (enhance the sensitivity of the timing violation) to read the digital value and check if the value was desired; the error was treated as an error or the evidence of an attack. The sensor was categorized on parity check, the basic method for error checks, and it can be easily integrated into LSI chips by designing multiple buffers and a few D flip-flops.
The above mentioned sensors are application-specialized ones, and they will perform effectively under suitable situations.
Memory
Memory writing is used to store the information inside the chip. There is a report on one-time-memory (OTM) designed on LSI chips. Fig. 9 illustrates the concept of OTM by voltage regulation. It utilized the MOS-capacitor breakdown phenomenon by applying a strong electric field to the gate to cause hard breakdown101, and then detected the resistance of MOS-capacitor to read the state. As it utilized the MOS transistor’s (or capacitor’s) gate-oxide anti-fuse (AF) characteristics, it can be categorized as AF-OTM. It was featured with the advantage of zero power-consumption until writing time; therefore, it was suitable for low-power systems. This type of OTM needed high voltage (depends on the process nodes) and the combination with charge pumps is mandatory. Phan et al. reported a 2-Kbit OTM cell array design based on standard 0.18 µm CMOS process102. Its applications have been estimated to be used as a smart RFID tag that will be important for IoT applications to recognize chip identifications. Chou et al. reported a large on-chip OTM using the 10 nm FinFET CMOS process103. As the memory capacity was dependent on the CMOS processes, large-memory implementation needed shrunk processes.
Fig. 9. Conception of anti-fuse one-time-memory. |
Another type of on-chip OTM was reported by He et al. based on diode-implementation104. A similar phenomenon was applied to this diode OTM, and its advantage was reduced cost by minimized fabrication processes.
Today, the dynamic-random-access-memory (DRAM) is widely used in computing fields as the main memory; however, it needs charges to store the data and is unsuitable for energy-harvesting systems as their power supplies are unstable and relatively small. Therefore, the DRAM for IoT should be set up with a battery to maintain the power supply. Zhu reviewed the challenges of DRAM for IoT applications, as the late of shrinking from the semiconductor processes105. However, the on-chip integrated memory devices are still limited, and further researches on the same are highly desired.
DATA TRANSFERS
Data transfers are necessary for standalone devices to receive the control signals or send the information obtained by the devices. Wireless communication includes device-level antenna designs and modulation-methods for transferring signals. At the device level, Kim et al. investigated the on-chip integrated antennas for wireless communications in 2000106. Four linear, meander, zigzag, dipole and looped antenna structures were evaluated, and the loop antenna was proven to be the best for antenna designs. Later, Moriyama et al. investigated the meander-structure on-chip antenna. This meander antenna was designed to reduce the antenna size for on-chip integration; the same group proposed a system-level verifications107. The proposed device was utilized for short-range wireless communication of mm-length as well as for applications using intra/inter-chip communications. The inside of the module was connected by inductive coupling technology, which enabled stacking of the chips108. For IoT applications, microswitch is an essential component for Tx/Rx regulation with low power consumption. Bhuiyan et al. proposed a fully integrated microswitch designed on 0.13 µm CMOS process for an operation frequency of 2.4 GHz109.
A technique known as ‘back-scattering’ occurs with low power consumption by utilizing the reflection properties of the wireless signals. In 2021, a new back-scattering method was proposed, which removed the internal power sources by receiving the power from a 24 GHz-band power transferring, and then relaying a 28-GHz wireless signal by beam-forming to transfer extremely-high-frequency (EHF) to the wide-areas. In the proposed system, the vector-summing phase shifter was adopted to adjust the arbitrary phase, which enabled beam-forming at EHF band110., 111..
For modulation, Bourdel et al. proposed the Federal Communications Commission (FCC) band ultra-wide-band (UWB) pulse generators designed on fully integration112. The proposed pulse generator corresponded to three modulations of on-off keying (OOK), pulse position and pulse interval, with the adoption of power spectral density (PSD) analysis-based sizing method. Therefore, the modulation mode can be switched by the pulse generator according to the application. Zhang et al. proposed a low-power 5G-oriented wireless communication system113. The concept of harmonic-selection technique is used, and the switchable three phases suppress the power consumption by strictly controlling the bandwidth when compared with the conventional multi-band phased-array receivers.
EXAMPLE AND FUTURES
As mentioned in Section 1, XR applications are related to IoT. Hosoi et al. demonstrated the pseudo-wind perception with four senses of visual, auditory, thermal and vibrotactile by adopting the head-mounted display (HMD) and belt-type device equipped on arms for thermal and vibrotactile sensing116. The combination of these devices and standalone chip will be necessary to realize rich XR experiments, especially for entertainments and further researches.
Congestion evaluation has been researched as a unique application of standalone devices by utilizing the channel state information (CSI)117. As a Wi-Fi network is available in many places, the CSI-based congestion evaluation is powerful with a privacy-secured method. Hernandez et al. developed a lightweight and standalone IoT device for CSI applications with the adoption of the commercial Wi-Fi tool. It enables low-cost and mobile CSI communication, and the application is available just by installing the developed software on the smart devices.
Another concept of IoT is related to the local-area community. This smaller area community, which is known as the smart-town (or smart-city), aims to build an IoT-implemented society and can be recognized as early-state IoT applications118., 119., 120.. Additionally, the IoT can be expanded to academic fields related to energy harvesting monitoring121. Damian et al. proposed a concept-level micro-grid power supply regulation circuit for low-power and low-voltage IoT devices122. The proposed circuit enabled the safe shutdown of IoT devices when the PV power supply was at undervoltage situations.
Some LSI chips aim to integrate MEMS components123. These MEMS components are especially important for robotics, vehicles and factories with large systems. The applications include sensor nodes such as molecular sensing, in which the standard CMOS-based devices are difficult to be followed124, or low-voltage RF switching125., 126..
IoT network management systems are required for the establishment of smart cities, including power supply, data processing and security. The concept of IoT, which refers to connecting everything to networks, always suffers from security issues such as eavesdropping, falsification or cyberattack. The framework of the secured IoT network is underdeveloped127, and these security issues are vital, especially for automobiles, power gridsand mobile medical devices (and many others) which are related to human lives.
Since it is difficult to obtain enough energy to drive all the components on LSI chips, the full specifications of standalone LSI chips are still under research, the LSI chip with embedded operating system (OS) will be necessary. The OS should operate under low power consumption; therefore, specialized OS must be developed, namely real-time operating systems (RTOSs). One of the future styles is known as smartdust128, which employs TinyOS to enable the processing of general information129. Today, there are many candidates appearing post TinyOS, including Contiki, FreeRTOS and RIOT. As of 2018, the most popular one is Contiki OS130. After evaluating the power consumption of FreeRTOS and RIOT, Challouf et al. concluded that RIOT is superior to FreeRTOS in terms of power efficiency131. Additionally, RIOT supports multi-threading processes and is advantageous for high-performance computing132 as the others support pseudo-multi-threading133-134.
From Fig. 1, it can be seen that the realization of smartdust will enhance human society with digital-rich styles. For implementation, a smaller area with low power consumption and tolerant wireless communication will be necessary, and energy sources must be chosen according to the applications (the location, availability of light or acoustic energy, and minimum power consumption of the devices). Outside the chips, reliability and security will be vital factors for supporting the lifeline of smart cities. It is believed that circuit-level components have been well researched, and the implementations on LSI chips and driving RTOS are the next goals for IoT realization. Further developments and researches for realizations are highly desired.
CONCLUSION
This article reviewed the current technologies of standalone LSI chips for IoT applications. The system is diverse, ranging from the power components including energy harvester, controller, and voltage regulator, to applications such as sensors and data transfer units. However, the complete specifications of the standalone LSI, which is known as smartdust, are still being investigated, and it is hoped further developments on realizations will be achieved in the future.
MISCELLANEA
Supplementary materials Supplementary material associated with this arti- cle can be found, in the online version, at 10.1016/j.chip.2023.100048.
Declaration of Competing Interests The authors declare no competing interests.
