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Realization of False Target Jamming Signal Based on Zedboard Hardware Platform |
LIU Yuntao1,3, LU Manjun2, ZHANG Wenxu1,3, HU Jianbo4 |
1. School of Information and Communication Engineering,Harbin Engineering University,Harbin 150001,Heilongjiang China;2. Shanghai Radio Equipment Research Institute,Shanghai 201109,China;3. Key Laboratory of Advanced Marine Communication and Information Technology, Ministry of Industry and Information Technology, Harbin Engineering University, Harbin 150001, Heilongjiang, China;4. 91411 troops of the Chinese People's
Liberation Army,Dalian 116041,Liaoning, China |
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Abstract With the development of radar jamming technology in electronic warfare, multi-false target jamming has become an important jamming style against radar. This paper uses Zedboard-based FPGA hardware platform to realize false target jamming signal. This method can be used in the processing of radar signal interference modulation part of DRFM system. DRFM system can achieve high-fidelity replication of radar signal. At the same time, for the characteristics of radar signal such as large bandwidth, variable modulation patterns, the method of intermittently sampling and transmitting jamming based on delay superposition is adopted to design and realize false target jamming signal, which can quickly and accurately generate jamming signal and greatly reduce the requirements of the hardware system. The verification results show that this method can realize false target jamming to radar signal.
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Received: 07 March 2022
Published: 21 December 2022
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[1] |
ZHANG Minghao, ZHANG Wenxu, LU Manjun. A Design of Comb Spectrum Jamming Waveform Based on Random Phase and Cyclic Superposition of Multi-frequency Points[J]. Air & Space Defense, 2023, 6(4): 74-79. |
[2] |
FANG Haisong, SI Weijian. Hardware Architecture Design of Two-dimensional Spectrum Peak Search Algorithm Based on FPGA[J]. Air & Space Defense, 2020, 3(1): 58-64. |
[3] |
XIAO Anhong,ZENG Hui,QIN Youyong,JIN Jin,ZHOU Junyi,GUO Wen,CHEN Junjie. Cross-Clock Domain Verification Practice of
NASPIC Communication Module Based on FPGA[J]. Journal of Shanghai Jiaotong University, 2019, 53(Sup.1): 84-87. |
[4] |
WANG Zhenyu (王振瑜), WU Xiaosheng * (吴校生), SHU Shengzhu (叔晟竹) . Resonance Characteristics of Piezoelectric Resonator Based on Digital Driving Circuit of Field-Programmable Gate Array
[J]. Journal of Shanghai Jiao Tong University (Science), 2019, 24(1): 1-6. |
[5] |
LI Gezi1,CHEN Xiaogang1,CHEN Houpeng1,JIAO Shengpin2. Logical Circuit Accelerated Computing for Phase Change Memory Based Storage System[J]. Journal of Shanghai Jiaotong University, 2018, 52(1): 90-95. |
[6] |
LI Siqing*(李四青), LIU Hua (刘华). Development of a Wireless Capsule Endoscope System Based on Field Programmable Gate Array[J]. Journal of shanghai Jiaotong University (Science), 2017, 22(2): 156-160. |
[7] |
WU Hao (吴昊), SHEN Guo-feng* (沈国峰), SU Zhi-qiang (苏志强), CHEN Ya-zhu (陈亚珠). A New Full Bridge High Intensity Focused Ultrasound Power System with Harmonic Cancellation[J]. Journal of shanghai Jiaotong University (Science), 2014, 19(6): 698-701. |
[8] |
LING Xiao-Feng, GONG Xin-Bao, JIN Rong-Hong. Efficient Implementation of Real-Time PFFT Processor Based on FPGA[J]. Journal of Shanghai Jiaotong University, 2012, 46(11): 1811-1815. |
[9] |
WANG Yanyan,YANG Jianguo,SONG BaoYu,ZHANG Kun . Knock Control Based on Discrete Wavelet Transform and FPGA [J]. Journal of Shanghai Jiaotong University, 2010, 44(10): 1367-1371. |
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