Fig. 1 Design concept of the on-chip micro temperature controllers. Schematics of temperature control through a cooling by a heat sink with an ultra-low intrinsic thermal resistance $R_{\text{th}}$ for high-power electronics, b heating by a microheater with an ultra-high $R_{\text{th}}$ and c controlling by a micro thermoelectric (TE) temperature controller with a widely controllable equivalent thermal resistance ${R}_{\text{th}}^{\text{ e}}$ for low-power electronics. Note that the heating effect in a mainly causes the temperature fluctuations in b and c through their shared substrate. d SEM images of the nanoporous carbon nanotube (CNT) film, graphene oxide (GO) nano membrane by dip-coating and dense TE film by sputtering, respectively. e Top view false-colour SEM image of micro temperature controller (μ-TCer), showing the lateral multilevel microstructures. f Close-up image of TE legs marked in e. g 3D schematic of the TCer in vacuum, composed of a TE temperature control circuit driven by working current I_w (blue arrow), and a Pt sensor to measure temperature and simulate low-power electronics using a heating current I_h (green arrow). h Schematic vertical multilayer nanostructures of the μ-TCer marked with a white circle in g

Fig. 2 Cooling performance characterization. a Dependence of temperature difference ΔT on working current I_w and heating current I_h of the μ-TCer with optimized geometric parameters. b $\Delta T_{{\text{c}}}^{ \max }$ (green) and $R_{\text{th}}$ (black) as a function of the section-to-length ratio (S/L) in a series of μ-TCers (NO.1–NO.8) and their fitting lines. c Comparisons of cooling performance of the previously reported micro TECs (square) and μ-TCers in this work (circle), including ${\Delta T}_{{\text{c}}}^{{\text{ max}}}$ (P_c = 0 W) and corresponding cooling temperature control capability η. Note that the colour bar indicates their intrinsic $R_{\text{th}}$ valves, detailed data and related references are provided in Tables S1 and S3

Fig. 3 Device thermoelectric performance. Temperature-dependent a experimental (data point) and calculated (line) maximum cooling temperature difference $\Delta T_{{\text{c}}}^{ \max }$, b dimensionless device figure of merit ZT_D. c Device Seebeck coefficient α, d thermal resistance R_th and e internal resistance R of the μ-TCers, NO.7 with dense TE films (green) and NO.9 with porous TE films (black), respectively. The inset in a shows the morphological details of the porous TE films

Fig. 4 Temperature control for low-power electronics. a Dependence of power consumption P of the thermostatic control for a ~ 70-μW component on T_s and T_a, detailed data in Fig. S8. b Power consumption P versus T_s (T_a = 350 K) marked by the horizontal white dotted line in a. c Average COP versus T_s over different temperature ranges from minimum ambient temperature ${T}_{\text{ a}}^{ \, {\text{min}}}$ to 360 K. d Heating power-dependent ${R}_{\text{th}}^{\text{ e}}$ and relative thermal resistance (${R}_{{{\text{th}}}}^{{\text{ e}}} /R_{\text{th}}$) under various I_w at 350 K

Fig. 5 Controllability and stability of the micro TE TCer. Cycling number-dependent control temperature results of the micro TE TCer using an alternating working current (− 0.5/1.85 mA) for heating and cooling, respectively. a Continuous test results (2 s heating and 2 s cooling). b Intermittent test results during a single cycle (~ 80 ms cooling)