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  • Review article
    Qianyu Zhang, Zirui Zhang, Ce Li, Renjing Xu, Dongliang Yang, Linfeng Sun
    Chip. 2023, 2(4): 100059-18. https://doi.org/10.1016/j.chip.2023.100059

    With the advent of the “Big Data Era”, improving data storage density and computation speed has become more and more urgent due to the rapid growth in different types of data. Flash memory with a floating gate (FG) structure is attracting great attention owing to its advantages of miniaturization, low power consumption and reliable data storage, which is very effective in solving the problems of large data capacity and high integration density. Meanwhile, the FG memory with charge storage principle can simulate synaptic plasticity perfectly, breaking the traditional von Neumann computing architecture and can be used as an artificial synapse for neuromorphic computations inspired by the human brain. Among many candidate materials for manufacturing devices, van der Waals (vdW) materials have attracted widespread attention due to their atomic thickness, high mobility, and sustainable miniaturization properties. Owing to the arbitrary stacking ability, vdW heterostructure combines rich physics and potential 3D integration, opening up various possibilities for new functional integrated devices with low power consumption and flexible applications. This paper provides a comprehensive review of memory devices based on vdW materials with FG structure, including the working principles and typical structures of FG structure devices, with a focus on the introduction of various high-performance FG memories and their versatile applications in neuromorphic computing. Finally, the challenges of neuromorphic devices based on FG structures are also discussed. This review will shed light on the design and fabrication of vdW material-based memory devices with FG engineering, helping to promote the development of practical and promising neuromorphic computing.

  • Review
    Yang Fan, Liu Zhaorui, Ding Xumin, Li Yang, Wang Cong, Shen Guozhen
    Chip. 2024, 3(2): 100086-34. https://doi.org/10.1016/j.chip.2024.100086

    As a typical representative of nanomaterials, carbon nanomaterials have attracted widespread attention in the construction of electronic devices owing to their unique physical and chemical properties, multi-dimensionality, multi-hybridization methods, and excellent electronic properties. Especially in the recent years, memristors based on carbon nanomaterials have flourished in the field of building non-volatile memory devices and neuromorphic applications. In the current work, the preparation methods and structural characteristics of carbon nanomaterials of different dimensions were systematically reviewed. Afterwards, in depth discussion on the structural characteristics and working mechanism of memristors based on carbon nanomaterials of different dimensions was conducted. Finally, the potential applications of carbon-based memristors in logic operations, neural network construction, artificial vision systems, artificial tactile systems, and multimodal perception systems were also introduced. It is believed that this paper will provide guidance for the future development of high-quality information storage, high-performance neuromorphic applications, and high-sensitivity bionic sensing based on carbon-based memristors.

  • Review
    Peng Huihui, Gan Lin, Guo Xin
    Chip. 2024, 3(2): 100093-17. https://doi.org/10.1016/j.chip.2024.100093

    Inspired by the structure and principles of the human brain, spike neural networks (SNNs) appear as the latest generation of artificial neural networks, attracting significant and universal attention due to their remarkable low-energy transmission by pulse and powerful capability for large-scale parallel computation. Current research on artificial neural networks gradually change from software simulation into hardware implementation. However, such a process is fraught with challenges. In particular, memristors are highly anticipated hardware candidates owing to their fast-programming speed, low power consumption, and compatibility with the complementary metal-oxide semiconductor (CMOS) technology. In this review, we start from the basic principles of SNNs, and then introduced memristor-based technologies for hardware implementation of SNNs, and further discuss the feasibility of integrating customized algorithm optimization to promote efficient and energy-saving SNN hardware systems. Finally, based on the existing memristor technology, we summarize the current problems and challenges in this field.

  • Research Article
    Deng Yao, Liu Shenghong, Li Manshi, Zhang Na, Feng Yiming, Han Junbo, Kapitonov Yury, Li Yuan, Zhai Tianyou
    Chip. 2024, 3(2): 100088-8. https://doi.org/10.1016/j.chip.2024.100088

    Two-dimensional metal chalcogenides have garnered significant attention as promising candidates for novel neuromorphic synaptic devices due to their exceptional structural and optoelectronic properties. However, achieving large-scale integration and practical applications of synaptic chips has proven to be challenging due to significant hurdles in materials preparation and the absence of effective nanofabrication techniques. In a recent breakthrough, we introduced a revolutionary allopatric defect-modulated Fe7S8@MoS2 synaptic heterostructure, which demonstrated remarkable optoelectronic synaptic response capabilities. Building upon this achievement, our current study takes a step further by presenting a sulfurization-seeding synergetic growth strategy, enabling the large-scale and arrayed preparation of Fe7S8@MoS2 heterostructures. Moreover, a three-dimensional vertical integration technique was developed for the fabrication of arrayed optoelectronic synaptic chips. Notably, we have successfully simulated the visual persistence function of the human eye with the adoption of the arrayed chip. Our synaptic devices exhibit a remarkable ability to replicate the preprocessing functions of the human visual system, resulting in significantly improved noise reduction and image recognition efficiency. This study might mark an important milestone in advancing the field of optoelectronic synaptic devices, which significantly prompts the development of mature integrated visual perception chips.

  • Research Article
    Jing Xu, Qian Cheng, Zheng Xiaodong, Nian Hu, Wang Chenquan, Tang Jie, Gu Xiaowen, Kong Yuechan, Chen Tangsheng, Liu Yichen, Sheng Chong, Jiang Dong, Niu Bin, Lu Liangliang
    Chip. 2024, 3(2): 100083-10. https://doi.org/10.1016/j.chip.2024.100083

    Building communication links among multiple users in a scalable and robust way is a key objective in achieving large-scale quantum networks. In a realistic scenario, noise from the coexisting classical light is inevitable and can ultimately disrupt the entanglement. The previous significant fully connected multiuser entanglement distribution experiments are conducted using dark fiber links, and there is no explicit relation between the entanglement degradations induced by classical noise and its error rate. Here, a semiconductor chip with a high figure-of-merit modal overlap is fabricated to directly generate broadband polarization entanglement. The monolithic source maintains the polarization entanglement fidelity of above 96% for 42 nm bandwidth, with a brightness of 1.2 × 107 Hz mW−1. A continuously working quantum entanglement distribution are performed among three users coexisting with classical light. Under finite-key analysis, secure keys are established and images encryption are enabled as well as quantum secret sharing between users. This work paves the way for practical multiparty quantum communication with integrated photonic architecture compatible with real-world fiber optical communication network.

  • Review
    Li Chengjun, Luo Yubo, Li Wang, Yang Boyu, Sun Chengwei, Ma Wenyuan, Ma Zheng, Wei Yingchao, Li Xin, Yang Junyou
    Chip. 2024, 3(2): 100096-13. https://doi.org/10.1016/j.chip.2024.100096

    With the development of 5G technology and increasing chip integration, traditional active cooling methods struggle to meet the growing thermal demands of chips. Thermoelectric coolers (TECs) have garnered great attention due to their rapid response, significant cooling differentials, strong compatibility, high stability and controllable device dimensions. In this review, starting from the fundamental principles of thermoelectric cooling and device design, high-performance thermoelectric cooling materials are summarized, and the progress of advanced on-chip TECs is comprehensively reviewed. Finally, the paper outlines the challenges and opportunities in TEC design, performance and applications, laying great emphasis on the critical role of thermoelectric cooling in addressing the evolving thermal management requirements in the era of emerging chip technologies.

  • Review article
    Kai Yang, Chenggong He, Jiming Fang, Xinhui Cui, Haiding Sun, Yansong Yang, Chengjie Zuo
    Chip. 2023, 2(4): 100058-26. https://doi.org/10.1016/j.chip.2023.100058

    This paper provides a comprehensive review of advanced radio frequency (RF) filter technologies available in miniature chip or integrated circuit (IC) form for wireless communication applications. The RF filter technologies were organized according to the timeline of their introduction, in conjunction with each generation of wireless (cellular) communication standards (1G to 5G). This approach enabled a clear explanation of the corresponding invention history, working principles, typical applications and future development trends. The article covered commercially successful acoustic filter technologies, including the widely used surface acoustic wave (SAW) and bulk acoustic wave (BAW) filters, as well as electromagnetic filter technologies based on low-temperature co-fired ceramic (LTCC) and integrated passive device (IPD). Additionally, emerging filter technologies such as IHP-SAW, suspended thin-film lithium niobate (LiNbO3 or LN) resonant devices and hybrid were also discussed. In order to achieve higher performance, smaller form factor and lower cost for the wireless communication industry, it is believed that fundamental breakthroughs in materials and fabrication techniques are necessary for the future development of RF filters.

  • Research Article
    Zhang Li-Hua, Liu Bang, Liu Zong-Kai, Zhang Zheng-Yuan, Shao Shi-Yao, Wang Qi-Feng, Ma Yu, Han Tian-Yu, Guo Guang-Can, Ding Dong-Sheng, Shi Bao-Sen
    Chip. 2024, 3(2): 100089-9. https://doi.org/10.1016/j.chip.2024.100089

    Detecting microwave signals over a wide frequency range is endowed with numerous advantages as it enables simultaneous transmission of a large amount of information and access to more spectrum resources. This capability is crucial for applications such as microwave communication, remote sensing and radar. However, conventional microwave receiving systems are limited by amplifiers and band-pass filters that can only operate efficiently in a specific frequency range. Typically, these systems can only process signals within a three-fold frequency range, which limits the data transfer bandwidth of the microwave communication systems. Developing novel atom-integrated microwave sensors, for example, radio-frequency (RF) chip-coupled Rydberg atomic receiver, provides opportunities for a large working bandwidth of microwave sensing at the atomic level. In the current work, an ultra-wide dual-band RF sensing scheme was demonstrated by space-division multiplexing two RF-chip-integrated atomic receiver modules. The system can simultaneously receive dual-band microwave signals that span a frequency range exceeding 6 octaves (300 MHz and 24 GHz). This work paves the way for multi-band microwave reception applications within an ultra-wide range by RF-chip-integrated Rydberg atomic sensor.

  • Review article
    Shiheng Yang, Jun Yin, Yueduo Liu, Zihao Zhu, Rongxin Bao, Jiahui Lin, Haoran Li, Qiang Li, Pui-In Mak, Rui P. Martins
    Chip. 2023, 2(2): 100051-10. https://doi.org/10.1016/j.chip.2023.100051

    This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator (VCO)-based phase-locked loops (PLLs) for clock generation in different applications. Particularly, the objective of the current work is to evaluate the required PLL performance among the fundamental metrics of power, jitter and area. An in-depth treatment of the mainstream PLL architectures and the associated design techniques enables them to be compared analytically and benchmarked with respect to their figure-of-merit (FoM). The paper also summarizes the key concerns on the selection of different circuit techniques to optimize the clock performance under different scenarios.

  • Research article
    Yan Li, Zhiling Wang, Zenghui Bao, Yukai Wu, Jiahui Wang, Jize Yang, Haonan Xiong, Yipu Song, Hongyi Zhang, Luming Duan
    Chip. 2023, 2(3): 100063-5. https://doi.org/10.1016/j.chip.2023.100063

    A non-classical light source is essential for implementing a wide range of quantum information processing protocols, including quantum computing, networking, communication and metrology. In the microwave regime, propagating photonic qubits, which transfer quantum information between multiple superconducting quantum chips, serve as building blocks for large-scale quantum computers. In this context, spectral control of propagating single photons is crucial for interfacing different quantum nodes with varied frequencies and bandwidths. Here a deterministic microwave quantum light source was demonstrated based on superconducting quantum circuits that can generate propagating single photons, time-bin encoded photonic qubits and qudits. In particular, the frequency of the emitted photons can be tuned in situ as large as 200 MHz. Even though the internal quantum efficiency of the light source is sensitive to the working frequency, it is shown that the fidelity of the propagating photonic qubit can be well preserved with the time-bin encoding scheme. This work thus demonstrates a versatile approach to realizing a practical quantum light source for future distributed quantum computing.

  • Research Article
    Tang Zhenyun, Wang Zhe, Song Zhigang, Zheng Wanhua
    Chip. 2024, 3(2): 100094-9. https://doi.org/10.1016/j.chip.2024.100094

    Tunneling-based static random-access memory (SRAM) devices have been developed to fulfill the demands of high density and low power, and the performance of SRAMs has also been greatly promoted. However, for a long time, there has not been a silicon based tunneling device with both high peak valley current ratio (PVCR) and practicality, which remains a gap to be filled. Based on the existing work, the current manuscript proposed the concept of a new silicon-based tunneling device, i.e., the silicon cross-coupled gated tunneling diode (Si XTD), which is quite simple in structure and almost completely compatible with mainstream technology. With technology computer aided design (TCAD) simulations, it has been validated that this type of device not only exhibits significant negative-differential-resistance (NDR) behavior with PVCRs up to 106, but also possesses reasonable process margins. Moreover, SPICE simulation showed the great potential of such devices to achieve ultralow-power tunneling-based SRAMs with standby power down to 10−12 W.

  • Research Article
    Hao Zifan, Zou Kai, Meng Yun, Yan Jun-Yong, Li Fangyuan, Huo Yongheng, Jin Chao-Yuan, Liu Feng, Descamps Thomas, Iovan Adrian, Zwiller Val, Hu Xiaolong
    Chip. 2024, 3(2): 100087-8. https://doi.org/10.1016/j.chip.2024.100087

    Superconducting nanowire single-photon detectors (SNSPDs) have become a mainstream photon-counting technology that has been widely applied in various scenarios. So far, most multi-channel SNSPD systems, either reported in literature or commercially available, are polarization sensitive, that is, the system detection efficiency (SDE) of each channel is dependent on the state of polarization of the to-be-detected photons. Here, we reported an eight-channel system with fractal SNSPDs working in the wavelength range of 930 to 940 nm, which are all featured with low polarization sensitivity. In a close-cycled Gifford-McMahon cryocooler system with the base temperature of 2.2 K, we installed and compared the performance of two types of devices: (1) SNSPD, composed of a single, continuous nanowire and (2) superconducting nanowire avalanche photodetector (SNAP), composed of 16 cascaded units of two nanowires electrically connected in parallel. The highest SDE among the eight channels reaches $96_{-5}^{+4}$%, with the polarization sensitivity of 1.02 and a dark-count rate of 13 counts per second. The average SDE for eight channels for all states of polarization is estimated to be 90 ± 5%. It is concluded that both the SNSPDs and the SNAPs can reach saturated, high SDE at the wavelength of interest, and the SNSPDs show lower dark-count (false-count) rates, whereas the SNAPs show better properties in the time domain. With the adoption of this system, we showcased the measurements of the second-order photon-correlation functions of light emission from a single-photon source based on a semiconductor quantum dot and from a pulsed laser. It is believed that this work will provide new choices of systems with single-photon detectors combining the merits of high SDE, low polarization sensitivity, and low noise that can be tailored for different applications.

  • Research article
    Yongqiang Du, Xun Zhu, Xin Hua, Zhengeng Zhao, Xiao Hu, Yi Qian, Xi Xiao, Kejin Wei
    Chip. 2023, 2(1): 100039-6. https://doi.org/10.1016/j.chip.2023.100039

    Silicon-based polarization-encoding quantum key distribution (QKD) has been extensively studied due to its advantageous characteristics of its low cost and robustness. However, given the difficulty of fabricating polarized independent components on the chip, previous studies have only adopted off-chip devices to demodulate the quantum states or perform polarization compensation. In the current work, a fully chip-based decoder for polarization-encoding QKD was proposed. The chip realized a polarization state analyzer and compensated for the BB84 protocol without the requirement of additional hardware, which was based on a polarization-to-path conversion method utilizing a polarization splitter-rotator. The chip was fabricated adopting a standard silicon photonics foundry, which was of a compact design and suitable for mass production. In the experimental stability test, an average quantum bit error rate of 0.59% was achieved through continuous operation for 10 h without any polarization feedback. Furthermore, the chip enabled the automatic compensation of the fiber polarization drift when utilizing the developed feedback algorithm, which was emulated by a random fiber polarization scrambler. Moreover, a finite-key secret rate of 240 bps over a fiber spool of 100 km was achieved in the case of the QKD demonstration. This study marks an important step toward the integrated, practical, and large-scale deployment of QKD systems.

  • Review article
    Haonan Chang, Jun Zhang
    Chip. 2023, 2(3): 100054-12. https://doi.org/10.1016/j.chip.2023.100054

    Cryogenic electronics refers to the devices and circuits operated at cryogenic temperatures (below 123.15 K), which are made from a variety of materials such as insulators, conductors, semiconductors, superconductors and topological materials. The cryogenic electronics are endowed with some unique advantages that cannot be realized in room temperature, including high computing speed, high power performance and so on. Choosing the appropriate refrigeration technology is critical for achieving the best performance of the cryogenic electronics. In this review, the cryogenic technology was divided into non-optical refrigeration and optical refrigeration, where non-optical refrigeration technologies are relatively conventional refrigeration technologies, while optical refrigeration is an emerging research field for the cooling of the chips. In the current work, the fundamental principles, applications and development prospects of the non-optical refrigeration was introduced, also the research history, fundamental principles, existing problems and application prospects of the optical refrigeration was thoroughly reviewed.

  • Review
    Liu Huan, Lin Dabin, Wang Puning, He Tingchao, Chen Rui
    Chip. 2024, 3(1): 100073-17. https://doi.org/10.1016/j.chip.2023.100073

    Solution-processed colloidal semiconductor nanocrystals (NCs) have become attractive materials for the development of optoelectronic and photonic devices due to their inexpensive synthesis and excellent optical properties. Recently, CdSe NCs with different dimensions and structures have achieved significant progress in photonic integrated circuits (PICs), including light generation (laser), guiding (waveguide), modulation, and detection on a chip. This article summarizes the development of CdSe NCs-based lasers and discusses the challenges and opportunities for the application of CdSe NCs in PICs. Firstly, an overview of the optical properties of CdSe-based NCs with different dimensions is presented, with emphasis on the amplified stimulated emission and laser properties. Then, the nanophotonic devices and PICs based on CdSe NCs are introduced and discussed. Finally, the prospects for PICs are addressed.

  • Research article
    Xiaosong Deng, Ning Kang, Zhiyong Zhang
    Chip. 2023, 2(4): 100064-18. https://doi.org/10.1016/j.chip.2023.100064

    The rise of quantum computing has prompted the interest in the field of cryogenic electronics. Carbon-based materials hold great promise in the area of cryogenic electronics due to their excellent material properties and emergent quantum effects. This paper introduces the advantages of carbon-based materials for cryogenic applications and reviews recent progress in carbon nanotubes and graphene for logic devices, sensors and novel quantum devices at cryogenic temperatures. Finally, the main challenges and extensive prospects for the further development of carbon-based cryoelectronics are summarized.

  • Research Article
    Saligram R., Raychowdhury A., Datta Suman
    Chip. 2024, 3(1): 100082-12. https://doi.org/10.1016/j.chip.2023.100082

    Low temperature complementary metal oxide semiconductor (CMOS) or cryogenic CMOS is a promising avenue for the continuation of Moore's law while serving the needs of high performance computing. With temperature as a control “knob” to steepen the subthreshold slope behavior of CMOS devices, the supply voltage of operation can be reduced with no impact on operating speed. With the optimal threshold voltage engineering, the device ON current can be further enhanced, translating to higher performance. In this article, the experimentally calibrated data was adopted to tune the threshold voltage and investigated the power performance area of cryogenic CMOS at device, circuit and system level. We also presented results from measurement and analysis of functional memory chips fabricated in 28 nm bulk CMOS and 22 nm fully depleted silicon on insulator (FDSOI) operating at cryogenic temperature. Finally, the challenges and opportunities in the further development and deployment of such systems were discussed.

  • Research article
    Qiwen Xue, Yuanke Zhang, Mingjie Wen, Xiaohu Zhai, Yuefeng Chen, Tengteng Lu, Chao Luo, Guoping Guo
    Chip. 2023, 2(4): 100065-8. https://doi.org/10.1016/j.chip.2023.100065

    The development of large-scale quantum computing has boosted an urgent desire for the advancement of cryogenic CMOS (cryo-CMOS), which is a promising scalable solution for the control and read-out interface of quantum bits. In the current work, 180 nm CMOS transistors were characterized and modeled down to 4 K, and the impact of low-temperature transistor performance variations on circuit design was also analyzed. Based on the proposed cryogenic model, a 180 nm CMOS-based 450 to 850 MHz clock generator operating at 4 K for quantum computing applications was presented. At the output frequency of 600 MHz, it achieved < 4.8 ps RMS jitter with 30 mW power consumption (with test buffer), corresponding to a −211.6 dB jitter-power FOM, which is suitable for providing a stable clock signal for the control and readout electronics of scalable quantum computers.

  • Research Article
    Xue Honglei, Peng Yue, Jing Qiushi, Zhou Jiuren, Han Genquan, Fu Wangyang
    Chip. 2024, 3(1): 100074-6. https://doi.org/10.1016/j.chip.2023.100074

    With major signal analytical elements situated away from the measurement environment, extended gate (EG) ion-sensitive field-effect transistors (ISFETs) offer prospects for whole chip circuit design and system integration of chemical sensors. In this work, a highly sensitive and power-efficient ISFET was proposed based on a metal-ferroelectric-insulator gate stack with negative capacitance-induced super-steep subthreshold swing and ferroelectric memory function. Along with a remotely connected EG electrode, the architecture facilitates diverse sensing functions for future establishment of smart biochemical sensor platforms.

  • Research article
    Chao Xin, Yaohui Yin, Bingqian Song, Zhen Fan, Yongli Song, Feng Pan
    Chip. 2023, 2(4): 100071-11. https://doi.org/10.1016/j.chip.2023.100071Get

    Two-dimensional ferromagnetic (2DFM) semiconductors (metals, half-metals, and so on) are important materials for next-generation nano-electronic and nano-spintronic devices. However, these kinds of materials remain scarce, “trial and error” experiments and calculations are both time-consuming and expensive. In the present work, in order to obtain the optimal 2DFM materials with strong magnetization, a machine learning (ML) framework was established to search the 2D material space containing over 2417 samples and identified 615 compounds whose magnetic orders were then determined via high-throughput first-principles calculations. With the adoption of ML algorithms, two classification models and a regression model were trained. The interpretability of the regression model was evaluated through Shapley Additive exPlanations (SHAP) analysis. Unexpectedly, it is found that Cr2NF2 is a potential antiferromagnetic ferroelectric 2D multiferroic material. More importantly, 60 novel 2DFM candidates were predicted, and among them, 13 candidates have magnetic moments of > 7μB. Os2Cl8, Fe3GeSe2, and Mn4N3S2 were predicted to be novel 2DFM semiconductors, metals, and half-metals, respectively. With the adoption of the ML approach in the current work, the prediction of 2DFM materials with strong magnetization can be accelerated, and the computation time can be drastically reduced by more than one order of magnitude.

  • Review article
    Yiqi Sun, Jiean Li, Sheng Li, Yongchang Jiang, Enze Wan, Jiahan Zhang, Yi Shi, Lijia Pan
    Chip. 2023, 2(1): 100031-22. https://doi.org/10.1016/j.chip.2022.100031

    Human nervous system, which is composed of neuron and synapse networks, is capable of processing information in a plastic, data-parallel, fault-tolerant, and energy-efficient approach. Inspired by the ingenious working mechanism of this miraculous biological data processing system, scientists have been devoting great efforts to artificial neural systems based on synaptic devices in recent decades. The continuous development of bioinspired sensors and synaptic devices in recent years have made it possible that artificial sensory neural systems are capable of capturing and processing stimuli information in real time. The progress of biomimetic sensory neural systems could provide new methods for next-generation humanoid robotics, human-machine interfaces, and other frontier applications. Herein, this review summarized the recent progress of synaptic devices and biomimetic sensory neural systems. Additionally, the opportunities and remaining challenges in the further development of biomimetic sensory neural systems were also outlined.

  • Research article
    Bo Liu, Yudi Zhao, YinFeng Chang, Han Hsiang Tai, Hanyuan Liang, Tsung-Cheng Chen, Shiwei Feng, Tuo-Hung Hou, Chao-Sung Lai
    Chip. 2023, 2(1): 100040-12. https://doi.org/10.1016/j.chip.2023.100040

    Implementing hardware primitives into cryptosystem has become a new trend in electronic community. Memristor, with intrinsic stochastic characteristics including the switching voltages, times and energies, as well as the fluctuations of the resistance state over time, could be a naturally good entropy source for cryptographic key generation. In this study, based on kinetic Monte Carlo Simulation, multiple Artificial Intelligence techniques, as well as kernel density map and time constant analysis, memristive spatiotemporal variability within graphene based conductive bridging RAM (CBRAM) have been synergistically analyzed to verify the inherent randomness of the memristive stochasticity. Moreover, the random number based on hardware primitives passed the Hamming Distance calculation with high randomness and uniqueness, and has been integrated into a Rivest-Shamir-Adleman (RSA) cryptosystem. The security of the holistic cryptosystem relies both the modular arithmetic algorithm and the intrinsic randomness of the hardware primitive (to be more reliable, the random number could be as large as possible, better larger than 2048 bits as NIST suggested). The spatiotemporal-variability-based random number is highly random, physically unpredictable and machine-learning-attack resilient, improving the robustness of the entire cryptosystem.

  • Research article
    Wenkai Zhang, Xueyi Jiang, Wentao Gu, Junwei Cheng, Hailong Zhou, Jianji Dong, Dongmei Huang, Xinliang Zhang
    Chip. 2023, 2(2): 100043-7. https://doi.org/10.1016/j.chip.2023.100043

    As an indispensable part to compensate for the signal crosstalk in fiber communication systems, conventional digital multi-input multi-output (MIMO) signal processor is facing the challenges of high computational complexity, high power consumption and relatively low processing speed. The optical MIMOenables the best use of light and has been proposed to remedy this limitation. However, the currently existing optical MIMO methods are all restricted to the spatial dimension, while the temporal dimension is neglected. Here, an on-chip spatial-temporal descrambler with four channels were devised and its MIMO functions were experimentally verified simultaneously in both spatial and temporal dimensions. The spatial crosstalk of single-channel descrambler and four-channel descrambler is respectively less than -21 dB and -18 dB, and the time delay is simultaneously compensated successfully. Moreover, a more universal model extended to mode-dependent loss and gain (MDL) compensation was further developed, which is capable of being cascaded for the real optical transmission system. The first attempt at photonic spatial-temporal descrambler enriched the varieties of optical MIMO, and the proposed scheme provided a new opportunity for all-optical MIMO signal processing.

  • Research article
    Jiawei Yang, Kaiyu Cui, Yidong Huang, Wei Zhang, Xue Feng, Fang Liu
    Chip. 2023, 2(2): 100045-8. https://doi.org/10.1016/j.chip.2023.100045

    Spectral imaging extends the concept of traditional color cameras to capture images across multiple spectral channels and has broad application prospects. Conventional spectral cameras based on scanning methods suffer from the drawbacks of low acquisition speed and large volume. On-chip computational spectral imaging based on metasurface filters provides a promising scheme for portable applications, but endures long computation time due to point-by-point iterative spectral reconstruction and mosaic effect in the reconstructed spectral images. In this study, on-chip rapid spectral imaging was demonstrated, which eliminated the mosaic effect in the spectral image by deep-learning-based spectral data cube reconstruction. The experimental results show that 4 orders of magnitude faster than the iterative spectral reconstruction were achieved, and the fidelity of the spectral reconstruction for the standard color plate was over 99% for a standard color board. In particular, video-rate spectral imaging was demonstrated for moving objects and outdoor driving scenes with good performance for recognizing metamerism, where the concolorous sky and white cars can be distinguished via their spectra, showing great potential for autonomous driving and other practical applications in the field of intelligent perception.

  • Review article
    Saravanan Yuvaraja, Vishal Khandelwal, Xiao Tang, Xiaohang Li
    Chip. 2023, 2(4): 100072-28. https://doi.org/10.1016/j.chip.2023.100072

    Wide-bandgap semiconductors exhibit much larger energy bandgaps than traditional semiconductors such as silicon, rendering them very promising to be applied in the fields of electronics and optoelectronics. Prominent examples of semiconductors include SiC, GaN, ZnO, and diamond, which exhibit distinctive characteristics such as elevated mobility and thermal conductivity. These characteristics facilitate the operation of a wide range of devices, including energy-efficient bipolar junction transistors (BJTs) and metal-oxide-semiconductor field-effect transistors (MOSFETs), as well as high-frequency high-electron-mobility transistors (HEMTs) and optoelectronic components such as light-emitting diodes (LEDs) and lasers. These semiconductors are used in building integrated circuits (ICs) to facilitate the operation of power electronics, computer devices, RF systems, and other optoelectronic advancements. These breakthroughs include various applications such as imaging, optical communication, and sensing. Among them, the field of power electronics has witnessed tremendous progress in recent years with the development of wide bandgap (WBG) semiconductor devices, which is capable of switching large currents and voltages rapidly with low losses. However, it has been proven challenging to integrate these devices with silicon complementary metal oxide semiconductor (CMOS) logic circuits required for complex control functions. The monolithic integration of silicon CMOS with WBG devices increases the complexity of fabricating monolithically integrated smart integrated circuits (ICs). This review article proposes implementing CMOS logic directly on the WBG platform as a solution. However, achieving the CMOS functionalities with the adoption of WBG materials still remains a significant hurdle. This article summarizes the research progress in the fabrication of integrated circuits adopting various WBG materials ranging from SiC to diamond, with the goal of building future smart power ICs.

  • Research article
    Qiaolv Ling, Penghui Dong, Yayan Chu, Xiaowen Dong, Jingye Chen, Daoxin Dai, Yaocheng Shi
    Chip. 2023, 2(4): 100061-8. https://doi.org/10.1016/j.chip.2023.100061

    A matrix-vector multiplication (MVM) optical signal processor based on mode division multiplexing (MDM) was proposed and demonstrated in the current work, which is composed of a mode multiplexer, a multimode beam splitter, a mode demultiplexer, a modulator array and combiners. In addition, the characteristics of MDM obviate the need for multiple wavelengths and therefore multiple laser light sources are unneeded, which greatly reduces the complexity and cost. A 4 × 4 MDM-MVM was realized on a standard silicon-on-insulator (SOI) platform. Combined with the off-chip light source and photodetectors (PDs), 4-level modulation has been demonstrated, and each level of the output signal could represent 2 bits of information.

  • Research article
    Yingshan Zhang, Huikai Xu, Yu Song, Yuqun Xu, Shuang Yang, Ziyue Hua, Shoukuan Zhao, Weiyang Liu, Guangming Xue, Yirong Jin, Haifeng Yu
    Chip. 2023, 2(4): 100067-8. https://doi.org/10.1016/j.chip.2023.100067

    The mitigation of dephasing poses a significant challenge to improving the performance of error-prone superconducting quantum computing systems. Here, the dephasing of a transmon qubit in a dispersive readout regime was investigated by adopting a Josephson traveling-wave parametric amplifier as the preamplifier. Our findings reveal that the potent pump leakage from the preamplifier may lead to severe dephasing. This could be attributed to a mixture of measurement-induced dephasing, ac Stark effect, and heating. It is showed that pulse-mode readout is a promising measurement scheme to mitigate qubit dephasing while minimizing the need for bulky circulators. Our work provides key insights into mitigating decoherence from microwave-pumped preamplifiers, which will be critical for advancing large-scale quantum computers.

  • Research article
    Zhen-Nan Tian, Feng Yu, Xu-Lin Zhang, Kai Ming Lau, Li-Cheng Wang, Jensen Li, C.T. Chan, Qi-Dai Chen
    Chip. 2023, 2(4): 100066-7. https://doi.org/10.1016/j.chip.2023.100066

    Exceptional points (EPs), which are typically defined as the degeneracy points of a non-Hermitian Hamiltonian, have been investigated in various physical systems such as photonic systems. In particular, the intriguing topological structures around EPs have given rise to novel strategies for manipulating photons and the underlying mechanism is especially useful for on-chip photonic applications. Although some on-chip experiments with the adoption of lasers have been reported, EP-based photonic chips working in the quantum regime largely remain elusive. In the current work, a single-photon experiment was proposed to dynamically encircle an EP in on-chip photonic waveguides possessing passive anti-parity-time symmetry. Photon coincidences measurement reveals a chiral feature of transporting single photons, which can act as a building block for on-chip quantum devices that require asymmetric transmissions. The findings in the current work pave the way for on-chip experimental study on the physics of EPs as well as inspiring applications for on-chip non-Hermitian quantum devices.

  • Review
    Meng Ruo-Ran, Liu Xiao, Jin Ming, Zhou Zong-Quan, Li Chuan-Feng, Guo Guang-Can
    Chip. 2024, 3(1): 100081-18. https://doi.org/10.1016/j.chip.2023.100081

    High-performance optical quantum memories serving as quantum nodes are crucial for the distribution of remote entanglement and the construction of large-scale quantum networks. Notably, quantum systems based on single emitters can achieve deterministic spin-photon entanglement, which greatly simplifies the difficulty of constructing quantum network nodes. Among them, optically interfaced spins embedded in solid-state systems, as atomic-like emitters, are important candidate systems for implementing long-lived quantum memory due to their stable physical properties and robustness to decoherence in scalable and compact hardware. To enhance the strength of light-matter interactions, optical microcavities can be exploited as an important tool to generate high-quality spin-photon entanglement for scalable quantum networks. They can enhance the photon collection probability and photon generation rate of specific optical transitions and improve the coherence and spectral purity of emitted photons. For solid-state systems, open Fabry-Pérot cavities can couple single emitters that are not in proximity to the surface, avoiding significant spectral diffusion induced by the interfaces while maintaining the wide tunability, which enables addressing of multiple single emitters in the frequency and spatial domain within a single device. This review described the characteristics of single emitters as quantum memories with a comparison to atomic ensembles, the cavity-enhancement effect for single emitters and the advantages of different cavities, especially fiber Fabry-Pérot microcavities. Finally, recent experimental progress on solid-state single emitters coupled with fiber Fabry-Pérot microcavities was also reviewed, with a focus on color centers in diamond and silicon carbide, as well as rare-earth dopants.

  • Review
    Liu Zijia, Gong Xunguo, Cheng Jinran, Shao Lei, Wang Chunshui, Jiang Jian, Cheng Ruiqing, He Jun
    Chip. 2024, 3(1): 100080-20. https://doi.org/10.1016/j.chip.2023.100080

    Two-dimensional (2D) van der Waals materials have attracted great interest and facilitated the development of post-Moore electronics owing to their novel physical properties and high compatibility with traditional microfabrication techniques. Their wafer-scale synthesis has become a critical challenge for large-scale integrated applications. Although the wafer-scale synthesis approaches for some 2D materials have been extensively explored, the preparation of high-quality thin films with well-controlled thickness remains a big challenge. This review focuses on the wafer-scale synthesis of 2D materials and their applications in integrated electronics. Firstly, several representative 2D layered materials including their crystal structures and unique electronic properties were introduced. Then, the current synthesis strategies of 2D layered materials at the wafer scale, which are divided into “top-down” and “bottom-up”, were reviewed in depth. Afterwards, the applications of 2D materials wafer in integrated electrical and optoelectronic devices were discussed. Finally, the current challenges and future prospects for 2D integrated electronics were presented. It is hoped that this review will provide comprehensive and insightful guidance for the development of wafer-scale 2D materials and their integrated applications.

  • Research Article
    Xu Ru, Chen Peng, Liu Xiancheng, Zhao Jianguo, Zhu Tinggang, Chen Dunjun, Xie Zili, Ye Jiandong, Xiu Xiangqian, Wan Fayu, Chang Jianhua, Zhang Rong, Zheng Youdou
    Chip. 2024, 3(1): 100079-8. https://doi.org/10.1016/j.chip.2023.100079

    GaN power electronic devices, such as the lateral AlGaN/GaN Schottky barrier diode (SBD), have received significant attention in recent years. Many studies have focused on optimizing the breakdown voltage (BV) of the device, with a particular emphasis on achieving ultra-high-voltage (UHV, > 10 kV) applications. However, another important question arises: can the device maintain a BV of 10 kV while having a low turn-on voltage (Von)? In this study, the fabrication of UHV AlGaN/GaN SBDs was demonstrated on sapphire with a BV exceeding 10 kV. Moreover, by utilizing a double-barrier anode (DBA) structure consisting of platinum (Pt) and tantalum (Ta), a remarkably low Von of 0.36 V was achieved. This achievement highlights the great potential of these devices for UHV applications.

  • Review article
    Takaya Sugiura, Kenta Yamamura, Yuta Watanabe, Shiun Yamakiri, Nobuhiko Nakano
    Chip. 2023, 2(3): 100048-13. https://doi.org/10.1016/j.chip.2023.100048

    In recent years, Internet of Things (IoT) has become more and more important owing to the rapid expansion of the number of computing devices and data sizes. The evolution of IoT requires low-power and self-operating devices to expand the coverage area of computing resources. The main components of IoT are the large-scale integration (LSI) chips, which take the function of implementing the energy harvesters, control units and applications. They exhibit different physics or phenomena, making it difficult to understand and design the entire system. The current work reviews the various methods for IoT applications by CMOS LSI chips, from the power components by energy harvesting to realistic applications with future outlooks.

  • Research article
    Hao Li, Ziheng Zhou, Yongzhi Zhao, Yue Li
    Chip. 2023, 2(2): 100049-9. https://doi.org/10.1016/j.chip.2023.100049

    Beam synthesizing antenna arrays are essentially demanded for on-chip millimeter wave and terahertz systems. In order to achieve a particular radiation beam, specific amplitude and phase distributions are required for all the array elements, which is conventionally realized through a properly designed feeding network. In the current work, a low-loss feeding network design approach based on epsilon-near-zero (ENZ) medium was proposed for large-scale antenna arrays with different beam requirements. Due to the infinite wavelength within the ENZ medium, a newly-discovered stair-like resonant mode was adopted for assigning a uniform phase distribution to each element, while the amplitudes and positions of these elements were optimized for generating particular beams. To implement the design philosophy in a low-loss manner, a hollow air-filled waveguide near cutoff frequency was employed to emulate the ENZ medium, and the bulk silicon microelectromechanical systems (MEMS) micromachining technology was utilized for chip-scale integration. As a specific example, a low-sidelobe antenna array at 60.0 GHz was designed, which realized an impedance bandwidth of 2.57%, a gain of 13.6 dBi and a sidelobe level as low as -20.0 dB within the size of 0.5 × 3.4λ02. This method is also compatible with a variety of applications, such as the high-directivity antenna array, non-diffractive Bessel beam antenna array, and so on. Based on this innovative concept of applying ENZ medium to the on-chip antenna array, it shows the advantages of simple structure and low loss for on-chip beam synthesis without complex lossy feeding networks.

  • Research article
    Zhongwang Wang, Xuefan Zhou, Xiaochi Liu, Aocheng Qiu, Caifang Gao, Yahua Yuan, Yumei Jing, Dou Zhang, Wenwu Li, Hang Luo, Junhao Chu, Jian Sun
    Chip. 2023, 2(2): 100044-8. https://doi.org/10.1016/j.chip.2023.100044

    State number, operation power, dynamic range and conductance weight update linearity are key synaptic device performance metrics for high-accuracy and low-power-consumption neuromorphic computing in hardware. However, high linearity and low power consumption couldn't be simultaneously achieved by most of the reported synaptic devices, which limits the performance of the hardware. This work demonstrates van der Waals (vdW) stacked ferroelectric field-effect transistors (FeFET) with single-crystalline ferroelectric nanoflakes. Ferroelectrics are of fine vdW interface and partial polarization switching of multi-domains under electric field pulses, which makes the FeFETs exhibit multi-state memory characteristics and excellent synaptic plasticity. They also exhibit a desired linear conductance weight update with 128 conductance states, a sufficiently high dynamic range of Gmax/Gmin > 120, and a low power consumption of 10 fJ/spike using identical pulses. Based on such an all-round device, a two-layer artificial neural network was built to conduct Modified National Institute of Standards and Technology (MNIST) digital numbers and electrocardiogram (ECG) pattern-recognition simulations, with the high accuracies reaching 97.6% and 92.4%, respectively. The remarkable performance demonstrates that vdW-FeFET is of obvious advantages in high-precision neuromorphic computing applications.

  • Review article
    Xiang Lan, Yingliang Cheng, Xiangdong Yang, Zhengwei Zhang
    Chip. 2023, 2(3): 100057-14. https://doi.org/10.1016/j.chip.2023.100057

    Moore's Law has been the driving force behind the semiconductor industry for several decades, but as silicon-based transistors approach their physical limits, researchers are searching for new materials to sustain this exponential growth. Two-dimensional transition metal dichalcogenides (TMDs), with their atomically thin structure and enticing physical properties, have emerged as the most promising candidates for downsizing and improving device integration. Emboldened by the direction of achieving large-area and high-quality TMDs growth, wafer-scale TMDs growth strategies have been continuously developed, suggesting that TMDs are poised to become a new platform for next-generation electronic devices. In this review, advanced synthesis routes and inherent properties of wafer-scale TMDs were critically assessed. In addition, the performance in electronic devices was also discussed, providing an outlook on the opportunities and challenges that lie ahead in their development.

  • Research Article
    Fan Huanrong, Raza Faizan, Mujahid Anas, Li Peng, Wang Yafen, Tang Haitian, Usman Muhammad, Li Bo, Li Changbiao, Zhang Yanpeng
    Chip. 2024, 3(1): 100077-11. https://doi.org/10.1016/j.chip.2023.100077

    The multi-Fano interference, which is obtained through the simultaneous acquisition of bright and dark states in different phase transitions of Eu3+ : BiPO4 (7 : 1, 6 : 1, 1 : 1, and 0.5 : 1) and Eu3+ : NaYF4 (1 : 1/4) crystals, were reported in this work. Multidressed spontaneous four-wave mixing and multidressed fluorescence (multiorder) were adopted to optimize the strong photon-phonon nested dressing effect, which results in more obvious multi-Fano interference. Firstly, the multi-Fano is produced through interference in continuous and multibound states. Secondly, five multi-Fano dips are originated from the nested five dressings (one photon and four phonons) under symmetrical splitting of 7F1 energy level. It is found that the pure H-phase (0.5 : 1) sample exhibits the strongest photon-phonon dressed effect (five Fano dips). Further, high-order non-Hermitian exceptional points in multi-Fano interference were investigated by adjusting the ratio of Rabi frequency to dephase rate through nested photon and phonon dressing. The experimental results are validated by theoretical simulations, which may be applied to designing optoelectronic devices such as non-Hermitian multi-Fano interferences (multichannel) router.

  • Research Article
    Liu Yarui, Wang Zhao, Xiang Zixuan, Wang Qikun, Hu Tianyang, Wang Xu
    Chip. 2024, 3(1): 100078-9. https://doi.org/10.1016/j.chip.2023.100078

    With the increasing number of ion qubits and improving performance of sophisticated quantum algorithms, more and more scalable complex ion trap electrodes have been developed and integrated. Nonlinear ion shuttling operations at the junction are more frequently used, such as in the areas of separation, merging, and exchanging. Several studies have been conducted to optimize the geometries of the radio-frequency (RF) electrodes to generate ideal trapping electric fields with a lower junction barrier and an even ion height of the RF saddle points. However, this iteration is time-consuming and commonly accompanied by complicated and sharp electrode geometry. Therefore, high-accuracy fabrication process and high electric breakdown voltage are essential. In the current work, an effective method was proposed to reduce the junction's pseudo-potential barrier and ion height variation by setting several individual RF electrodes and adjusting each RF voltage amplitude without changing the geometry of the electrode structure. The simulation results show that this method shows the same effect on engineering the trapping potential and reducing the potential barrier, but requires fewer parameters and optimization time. By combining this method with the geometrical shape-optimizing, the pseudo-potential barrier and the ion height variation near the junction can be further reduced. In addition, the geometry of the electrodes can be simplified to relax the fabrication precision and keep the ability to engineer the trapping electric field in real-time even after the fabrication of the electrodes, which provides a potential all-electric degree of freedom for the design and control of the two-dimensional ion crystals and investigation of their phase transition.

  • Research article
    Yu Guo, Shuming Cheng, Xiao-Min Hu, Bi-Heng Liu, Yun-Feng Huang, Chuan-Feng Li, Guang-Can Guo
    Chip. 2023, 2(1): 100041-7. https://doi.org/10.1016/j.chip.2023.100041

    Incompatible measurements are of fundamental importance to revealing the peculiar features of quantum theory, and are also useful resources in various quantum information tasks. In this work, we investigate the quantum incompatibility of mutually unbiased bases (MUBs) within the operational framework of quantum resource theory, and report an experimental validation via the task of state discrimination. In particular, we construct an experimentally friendly witness to detect incompatible MUBs, based on the probability of correctly discriminating quantum states. Furthermore, we prove that the noise robustness of MUBs can be retrieved from violating the above witness. Finally, we experimentally test the incompatibility of MUBs of dimensionality ranging from 2 to 4, and demonstrate that it is more robust to noise, as either the dimensionality of measurements or the number of MUBs increases. Our results may aid the exploration of the essential roles of incompatible measurements in both theoretical and practical applications in quantum information.

  • Review article
    Luming Wang, Pengcheng Zhang, Zuheng Liu, Zenghui Wang, Rui Yang
    Chip. 2023, 2(1): 100038-15. https://doi.org/10.1016/j.chip.2023.100038

    With increasing challenges towards continued scaling and improvement in performance faced by electronic computing, mechanical computing has started to attract growing interests. Taking advantage of the mechanical degree of freedom in solid state devices, micro/nano-electromechanical systems (MEMS/NEMS) could provide alternative solutions for future computing and memory systems with ultralow power consumption, compatibility with harsh environments, and high reconfigurability. In this review, MEMS/NEMS-enabled memories and logic processors were surveyed, and the prospects and challenges for future on-chip mechanical computing were also analyzed.

  • Research article
    Yali Ma, Yiwen Li, He Wang, Mengke Wang, Jun Wang
    Chip. 2023, 2(1): 100032-10. https://doi.org/10.1016/j.chip.2022.100032

    Flexible photodetectors (PDs) comprised of low-dimensional organic-inorganic hybrid perovskites with perovskite quantum dots are expected to be the next generation wearable optoelectronic devices. A flexible Vis-NIR PD which contains 2D Dion-Jacobson (DJ) perovskite (4AMP)(MA)2Pb3I10 (4AMP = 4-(aminomethyl)piperidinium, MA = methylammonium) (n3) and micro concentration of CsPbI3 perovskite quantum dots (QDs) layered heterostructures was designed and synthesized in the current work. Controlled by the optimal concentration of QDs, the device response under 660 nm light was increased to 615%. The device combination as per mass of QDs exhibited strong photosensitivity and high-power output. The band gap between the two is minimal, which formed a matching structure and lowered the energy barrier of carrier transport process. QDs layer filled the gap of perovskite film, forming an almost defect-free heterostructure. QDs layer isolated water and passivated the perovskite layer, which therefore contributed to the high-performance of optoelectronic devices. Under the optimal concentration of QDs with up to 5000 bending cycles and different bending angles, the degradation of PDscouldbe ignored, and the devices tended to show a self-healing phenomenon with increasing bending cycles. The optimized strategy will be conducive to developing flexible, wearable, high-performance and low-cost PDs.