Integrated Circuits and Systems >
The Decomposition and Combination Paradigms of Chiplet-Based Integrated Chips
YING WANG, (Member, IEEE) |
YUJIEWANG, (Member, IEEE) |
HAOBO XU, (Member, IEEE) |
HUAWEI LI, (Senior Member, IEEE) |
XIAOWEI LI, (Senior Member, IEEE) |
QI LIU, (Member, IEEE) |
YINHE HAN, (Senior Member, IEEE) |
Received date: 2024-04-24
Revised date: 2024-06-16
Accepted date: 2024-07-15
Online published: 2024-11-27
Supported by
National Natural Science Foundation of China (NSFC) under Grant(92373206)
National Natural Science Foundation of China (NSFC) under Grant(62222411)
National Natural Science Foundation of China (NSFC) under Grant(62025404)
National Key Research and Development Program of China under Grant(2023YFB4404400)
Due to the waning of Moore’s Law, the conventional monolithic chip architectural design is confronting hurdles such as increasing die size and skyrocketing cost. In this post-Moore era, the integrated chip has emerged as a pivotal technology, gaining substantial interest from both the academia and industry. Compared with monolithic chips, the chiplet-based integrated chips can significantly enhance system scalability, curtail costs, and accelerate design cycles. However, integrated chips introduce vast design spaces encompassing chiplets, inter-chiplet connections, and packaging parameters, thereby amplifying the complexity of the design process. This paper introduces the Optimal Decomposition-Combination Theory, a novel methodology to guide the decomposition and combination processes in integrated chip design. Furthermore, it offers a thorough examination of existing integrated chip design methodologies to showcase the application of this theory.
Key words: Chiplet; integrated chip; design methodology
FUPING LI , YING WANG , MEIXUAN LU , YUTONG ZHU , HAORAN WANG , ZHUN ZHAO , JUNPEI HUANG , XIAOTONG WEI , XIHAO LIANG , YUJIE WANG , HAOBO XU , HUAWEI LI , XIAOWEI LI , QI LIU , MING LIU , NINGHUI SUN , YINHE HAN . The Decomposition and Combination Paradigms of Chiplet-Based Integrated Chips[J]. Integrated Circuits and Systems, 2024 , 1(1) : 18 -30 . DOI: 10.23919/ICS.2024.3451428
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