The multiport interferometric technology holds significant promise as a versatile transceiver solution for next-generation wireless systems. Considerable progress has been made in exploring and developing this technology for RF front-end circuits and systems, including transmitters, receivers, and fully integrated transceivers. Its architecture distinguishes itself through several key advantages, namely, low power requirements for local oscillator (LO), cost-effectiveness, structural simplicity, wideband operation, and appreciable suitability for millimeter-wave (mmW) and terahertz (THz) applications. A particularly compelling feature of this technology is its inherent linear interference-based operation, which allows for a unified circuit topology to be used interchangeably as both a transmitter and a receiver. This versatility makes it an attractive candidate for addressing the growing demand for multifunctional wireless system design. This review article presents a comprehensive overview of the ongoing evolution of multiport interferometric technology. Various architectures are holistically examined through practical examples, with an emphasis on technical attributes, design innovations, and application scenarios. Recent advancements are highlighted, showcasing key research milestones and achievements in the field. The article also outlines future research directions and developmental prospects in the context of emerging wireless applications. As wireless systems increasingly require integrated capabilities—combining communication, sensing, and imaging—the adoption of multiport interferometric technology is poised to play a pivotal role in enabling this convergence. Its continued advancement is expected to drive innovation across a broad spectrum of next-generation wireless platforms.

Ultra-low-voltage SRAM is an indispensable component that is increasingly adopted in energyefficient computing systems. However, it comes at the cost of increased sensitivity to soft errors. To address this issue, bit-interleaving SRAM is widely used to mitigate soft errors. But it suffers from half-select disturbance. Previous works address such disturbance by using a dedicated write port or enhanced write assist scheme. However, these works may decrease write margin, induce high cell-level write latency, or incur architecture-level time/timing overhead. In this paper, we develop a high-speed bit-interleaving half-select disturb-free memory with data-aware 10T SRAM. First, we present an isolated and decoupled topology with dedicated write control to improve stability. Second, we present a data-aware write path with enhanced write-ability that effectively reduces the write access time. A 40-nm 4-Kb test chip has been fabricated to validate the optimizations above. Measurement results show that our half-select disturb-free test chip achieves a peak operating frequency of 25 MHz and an energy consumption of 0.168 fJ/bit with a supply voltage of 0.35 V. Compared with the state-of-the-art designs, it has achieved a speed up of 2.72× and an energy saving of 93.8%.

This paper describes an efficient fully programmatic and automated post-layout simulationbased optimization method for analog designs. The proposed methodology is developed to achieve the targeted performance objectives efficiently, that is, with reduced number of iterations and less simulation time, compared to currently predominantly manual design procedures. The efficiency of method is achieved through utilization of expert knowledge at every step of the proposed design process. The expert knowledge is supplied by formalizing the expression of design problems as nested functions, partitioning the design problem in both electrical and physical domains and by selection of starting point for the optimization. The circuit dependencies captured by the nested functions are augmented with backpropagation, similarly as in machinelearning. The proposed methodology provides a fully automated procedure for analog designs that incorporates extracted layout parasitic effects in all phases of the design process without human-in-the-loop. The effectiveness of the methodology is demonstrated with four example circuits: an inverter, a true single-phase clock flip-flop, a source follower, and a bootstrapped sampling switch. The variety of examples represent increasingly complex systems with increasing number of parameters, demonstrating capability of providing analog building blocks from specification to physical implementation without designer intervention.

Resistance Random Access Memory (ReRAM) crossbar arrays have been used in compute in-memory (CIM) application owing to its high bit-density, non-volatility, and capability to perform multiplyaccumulate (MAC) calculations efficiently. The expansion of the size of the crossbars has led to the emerging challenge of high IR voltage drop and more complex logic control devices. In this paper, we propose a progressive weight pruning strategy based on gradient sensitivity analysis to reduce redundant parameters and enhance overall sparsity. Building upon this sparsity-enhanced structure, we further introduce two complementary weight quantization-mapping methods tailored for high-bit and low-bit quantization scenarios. The proposed method utilizes group quantization for clustering to merge weights in higher bits and leverages differential properties to conduct spectral clustering for merging weights in lower bits. Experimental results indicate notable savings in crossbar resources with minimal loss of precision. Moreover, we designed a carrier board-FPGA testing platform and deployed a neural network on a 32×32 size ReRAM crossbar. The results show that the proposed algorithm saves 42% of units, and the recognition accuracy of the MNIST dataset is within an acceptable range (91.5% to 88.3%).

As computational complexity continues to increase, effectively designing a computation-inmemory (CIM) architecture has become a crucial task. In such an architecture, errors may occur due to factors such as voltage drift. This work focuses on designing a simulation framework for In-Situ error correction of multi-bit memory-in-computing circuits. The research concentrates on In-Situ error correction techniques, allowing the system to instantly detect and correct errors during memory or computational operations at the same location where data is being processed and stored. The primary goal of this work is to explore how to minimize the impact of these errors on model accuracy. In constructing the simulation environment, multi-bit weights are decomposed, and 2D convolutions are decomposed into matrix multiplications, then mapped onto the CIM architecture. Based on this framework, this work further analyzes hardware errors in CIM, including the causes of errors, statistical characteristics, and the impact of extreme error values on accuracy. Furthermore, we introduce and deeply analyze clamping as an error correction technique. Through a series of simulations, we came to the following clear conclusion: To maximize hardware efficiency and accuracy correction effects, special attention must be paid to high-bit weights and the protection of sensitive convolutional layers. In addition, reasonable setting of clamping threshold and appropriate array-based output grouping strategy are also indispensable. These strategies provide clear optimization directions for neural networks in specific application scenarios. After considering the above strategies and optimizing, the model accuracy can reach a maximum of 73.8%, which is close to the baseline of 75.8%. Considering that the protection circuit area is reduced by 50%, this result shows excellent benefits.