Computing-in-memory (CIM) offers a promising solution to the memory wall issue. Magnetoresistive random-access memory (MRAM) is a favored medium for CIM due to its non-volatility, high speed, low power, and technology maturity. However, MRAM has continuously encountered the challenge of an insufficient high-resistance state (HRS) to low-resistance state (LRS) ratio, which affects the result accuracy of CIM. In this paper, based on SOT devices, we propose a 5T2M bit-cell structure that increases the high-to-low current ratio by modulating the sub-threshold operation region. Besides, by jointly using high-resistance devices (M_ level), the power consumption of the bit-cell array can be significantly reduced. Simultaneously, we have designed a compatible multi-bit implementation and macro architecture to support AI edge inference acceleration. This work was simulated under a 40-nm foundry process and a physically verified SOT-MTJ model. The results show that under the same high-to-low resistance ratio, a 52.6× high-to-low current ratio can be achieved, along with a 38.6%-98% bit-cell array power reduction.
This paper presents a single-inductor-multiple-output (SIMO) buck/boost/buck-boost converter for wearable electronic devices.Aiming at high light-load efficiency and low ripple, the converter applies fully asynchronous burst mode control. The circuit enters sleep mode intermittently during light loads, significantly reducing static power consumption. The peak inductor current is fixed, effectively limiting the maximum output ripple. The converter features three conversion modes: buck, boost, and auto-gain buck-boost. DC analysis is conducted to derive expressions for output ripple and maximum load in relation to the peak inductor current. AC stability analysis is performed with small signal perturbation and linearization methods, proving the stability of all three modes. Measured results indicate that the converter achieves a peak efficiency of 91.0% at an output power of 77.5 mW. The maximum output ripple is 27.0 mV, and the overshoot or undershoot during load transients is not observed. Compared with existing converters, it exhibits higher efficiency and lower ripple, along with a fast load transient response, offering a highly efficient power management solution for wearable devices.
This paper presents a highly integrated wearable electrochemical sensor chip for sweat monitoring, incorporating both a current readout circuit and a programmable excitation waveform generator circuit. The chip is fabricated using a 0.11 μm standard CMOS process. The design utilizes a high-resolution and wide dynamic range current readout circuit for multimodality electrochemical sensing. A bidirectional current sensing potentiostat, based on a cascode current mirror, is presented. The circuit achieves bidirectional current sensing while isolating the sensing electrode from the subsequent circuitry, enhancing its versatility for various electrochemical measurement techniques. Additionally, the implementation of a current feedback loop, in conjunction with an automatic amplitude control method and a current-mode digital-to-analog converter, not only extends the dynamic range of the input current but also effectively eliminates the background currents. This design achieves 101 dB current dynamic range and 123 pA current resolution in the detection current range of ±15 μA with an R2 linearity of 0.9999. It also attains a nonlinearity of 0.07%, ensuring minimal distortion. The current readout circuit consumes 12 μA of static current from a 1.5 V supply.
This paper presents a fully digital foreground calibration method for pipeline-SAR analog-todigital converters (ADCs) using sine-fit based on the Extended Kalman Filter (EKF). The sine-fit technique provides a reference output, while an adaptive Least Mean Square (LMS) algorithm iteratively adjusts the reconstruction weights to correct mismatches and nonlinearities. The EKF significantly reduces hardware complexity by enabling real-time estimation without requiring extensive data storage. A modeled 12-bit pipeline-SAR ADC is used to evaluate the method’s effectiveness. Simulation results demonstrate that the proposed calibration scheme improves the spurious-free dynamic range (SFDR) and signal-to-noise-anddistortion ratio (SNDR) by 33.6 dB and 18.8 dB, respectively.
The evolution of 5G and beyond wireless networks has intensified the demand for millimeterwave technology to support high-throughput applications. This paper introduces a novel energy-efficient digital beamforming receiver architecture that integrates multi-stage noise-shaping (MASH) delta-sigma modulators (DSMs) with bit-stream processing (BSP), effectively addressing the significant propagation losses and dynamic electromagnetic interference associated with millimeter-wave (mm-wave) systems. The novel architecture achieves enhanced dynamic range without increasing signal bit-width, thereby ensuring low power consumption and a compact design. Unlike traditional analog and hybrid beamforming methods, the proposed approach utilizes digital-domain processing for precise beamforming, simplified local oscillator networks, and improved integration. System-level simulations with a 9-antenna beamforming receiver array demonstrate the architecture’s capability for accurate beamforming across angles from 30° to 150° and effective dual-target detection. Furthermore, the P2S-BSP architecture reduces digital circuitry area by 50% compared to previous implementations while maintaining energy efficiency. These advancements highlight the proposed architecture as a scalable solution for future mm-wave applications, including intelligent transportation systems, radar, and high-density mobile networks.
SPHINCS+ is a hash-based digital signature scheme that has been selected for post-quantum cryptography(PQC) standardization announced by the U.S. National Institute of Standards and Technology (NIST) in 2022. Although SPHINCS+ offers significant security against quantum attacks, its relatively slow computation times present a major obstacle to its practical deployment. To address this challenge, improving the computational efficiency of SPHINCS+ becomes a critical task. The cryptographic operations in SPHINCS+ rely on tweakable hash functions, with various hash algorithms available for selection. Among these, SHA-3 stands out as a widely adopted and NIST-standardized hash function, making it a preferred choice for implementation in SPHINCS+. In this work, we propose a dedicated coprocessor that integrates a SHA-3 accelerator along with its associated peripheral structure. This coprocessor is designed to extend the RISC-V instruction set by incorporating seven custom instructions, enabling efficient software-hardware co-acceleration. Furthermore, we investigate the parallelizable components within SPHINCS+, specifically the FORS and WOTS+ Algorithms, to identify means for optimization. By leveraging thread-level parallelism through multi-core programming, we achieve significant improvements in performance. To validate the design, synthesis is performed using TSMC 28-nm CMOS technology at 800 MHz. Compared to the benchmark results from the ARM Cortex-M4 processor, our approach achieves an impressive 23.1× speedup in the overall single-core performance of SPHINCS+, with an additional 3.4× speedup for the verification process by utilizing multi-core acceleration.
Since the discovery of speculative execution attacks based on side channels, there has been a long history of research on their attack mechanisms and defense principles. To explore TLB side channels, we constructed a System-on-Chip (SoC) centered around the XuanTie C910 processor on a Virtex UltraScale+ HBM VCU128 FPGA and ran the Linux operating system on this platform. We successfully implemented the Spectre-v1 attack targeting the multi-level TLB structure of the XuanTie C910 processor, identifying the second-level TLB as the primary target of the attack. In addition, we proposed a defense mechanism called TLBshield-v1, which employs a 50-percent block rate policy on the write-back channel from the Page Table Walker to the second-level TLB, thereby mitigating all attacks based on the second-level TLB. We tested a 50-percent block rate policy, which reduced the success rate of the Spectre-v1 attack from 100 percent to 55.7 percent, with a performance overhead of only 1.77 percent. Furthermore, we designed TLBshield-v2, with different block rates of second-level TLB, tested their corresponding performance overheads and security implications, and introduced a normalized evaluation metric, Security-Versus-Performance to determine the optimal design strategy that balances performance overhead and security under varying security requirements.
Control flow integrity (CFI) plays an important role in defending against code reuse attacks (CRA). It protects the program’s control flow from being hijacked by restricting control flow transfers during execution. Specifically, backward-edge CFI safeguards return addresses to mitigate Return-Oriented Programming (ROP) attacks. In this work, we implement a backward-edge CFI mechanism that employs the Advanced Encryption Standard (AES) for cryptographic protection of return addresses. We utilize the gem5 simulator for architectural modeling and evaluation. Additionally, we design a dedicated AES hardware accelerator and integrate it into the system through gem5+RTL co-simulation. The AES accelerator is synthesized under TSMC 28 nm technology, which can work at 1GHz, with an area of 10045 μm2 and a power consumption of 1.31 mW. Experimental results indicate that the performance overhead of the backward-edge CFI scheme is less than 0.1%.
