Integrated Circuits and Systems >
An Efficient Multiplier-Less ProcessingElement on Power-of-2 Dictionary-Based Data Quantization
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Jiaxiang Li (Student Member, IEEE) received the B.S. degree in microelectronic science and engineering from Sichuan University, Chengdu, China, in 2019, and the M.S. degree in electronic engineering (circuit and system) from the University of California at Irvine, Irvine, CA, USA, in 2021. He is currently working toward the Dr.Eng. degree with Waseda University, Tokyo, Japan. His research interests include energy efficient digital circuit and neural network hardware accelerator design. |
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Masao Yanagisawa (Member, IEEE) received the B.Eng., M.Eng., and Dr. Eng. degrees in electrical engineering from Waseda University, Tokyo, Japan, in 1981, 1983, and 1986, respectively. From 1986 to 1987, he was with the University of California at Berkeley, Berkeley, CA, USA. He joined Takushoku University, in 1987. He joined Waseda University, in 1991, where he is currently a Professor with the Faculty of Science and Engineering. His research interests include combinatorics and graph theory, computational geometry, LSI design and verification, and bioinformatics. |
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Youhua Shi (Member, IEEE) received the B.S. and M.S. degrees in electric engineering from Southeast University, Nanjing, China, in 1999 and 2002, respectively, and the Dr.Eng. degree in electronics, information, and communication engineering from Waseda University, Tokyo, Japan, in 2005. He is currently a Professor with the Faculty of Science and Engineering, Waseda University. His research interests include various aspects of integrated system design, such as design-for-reliability, energy harvesting, and intelligent system design. |
Received date: 2024-02-28
Revised date: 2024-05-14
Accepted date: 2024-06-27
Online published: 2024-11-27
Supported by
Waseda University Open Imnovation Ecosystem Program for Pionring Research (W-SPRING) underGrant umber(JPMISP2128)
The large-scale neural networks have brought incredible shocks to the world, changing people's lives and offering vast prospects. However, they also come with enormous demands for computational power and storage pressure, the core of its computational requirements lies in the matrix multiplication units dominated by multiplication operations. To address this issue, we propose an area-power-efficient multiplier-less processing element (PE) design. Prior to implementing the proposed PE, we apply a power-of-2 dictionary-based quantization to the model and effectiveness of this quantization method in preserving the accuracy of the original model is confirmed. In hardware design, we present a standard and one variant ‘bi-sign’ architecture of the PE. Our evaluation results demonstrate that the systolic array that implement our standard multiplier-less PE achieves approximately 38% lower power-delay-product and 13% smaller core area compared to a conventional multiplication-and-accumulation PE and the bi-sign PE design can even save 37% core area and 38% computation energy. Furthermore, the applied quantization reduces the model size and operand bit-width, leading to decreased on-chip memory usage and energy consumption for memory accesses. Additionally, the hardware schematic facilitates expansion to support other sparsity-aware, energy-efficient techniques.
JIAXIANG LI , MASAO YANAGISAWA , YoUHUA SH . An Efficient Multiplier-Less ProcessingElement on Power-of-2 Dictionary-Based Data Quantization[J]. Integrated Circuits and Systems, 2024 , 1(1) : 53 -62 . DOI: 10.23919/ICS.2024.3423850
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