Integrated Circuits and Systems >

2024 , Vol. 1 >Issue 4: 206 - 213

DOI: https://doi.org/10.23919/ICS.2024.3505092

Original article

A Dynamic Comparator With Cross-Coupled Pre-Amplifier With < 160 ps Delay and 81 fJ.ns EDP

  • NIDHI SHARMA , 1 ,
  • VINAYAK HANDE 2 ,
  • DEVARSHI MRINAL DAS 1
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  • 1 Indian Institute of Technology Ropar, Rupnagar 140001, India
  • 2 Research and Development Division ATV, Infineon Technologies AG, 9524 Villach, Europastraße 8, Austria

CORRESPONDING AUTHOR: NIDHI SHARMA (e-mail: ).

Received date: 2024-10-19

  Revised date: 2024-11-13

  Accepted date: 2024-11-19

  Online published: 2025-01-09

Supported by

the Anusandhan National Research Foundation of India under Grant CRG/2021/007283 for Tapeout and MeitY(C2S programme)

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Abstract

A low-power, high-speed dynamic comparator with the addition of a cross-coupled pair in the pre-amplifier stage, followed by a strong-arm latch, is presented. The proposed modification increases the pre-amplifier's differential and common-mode gains, improving the latch's differential and common-mode input voltage, resulting in faster regeneration with 22% speed improvement as compared to conventional comparator at small input differential voltages ( Vi,id ). The proposed technique boosts the comparator's speed and helps achieve 21% lower energy per conversion delay product (EDP) compared to the literature. Analytical modeling of the delay that proves the improvement in the speed of the proposed comparator is also presented and verified with the simulation results. The proposed comparator's delay is insensitive to the common-mode voltage (Vi,cm ). The proposed comparator is fabricated in 180-nm CMOS technology and measurement shows less than 160 ps relative CLK-Q delay with 81 fJ.ns EDP and 0.8 mV input-referred rms noise with 1.8 V supply. To demonstrate the scalability of the proposed technique to advanced technology nodes, the proposed design is also simulated in 65-nm CMOS technology with a 1.1 V supply for 5 GHz frequency. For Vi,cm of 0.3 V and Vi,id of 1 mV and 10 mV, the proposed comparator exhibits a 40.69 ps and 32.41 ps delay and has 3.74 fJ.ns and 2.78 fJ.ns EDP respectively.

Key words： Cross-coupled pair; double-tail comparator; dynamic comparator; high-speed; low-power; triple-tail comparator.

Cite this article

NIDHI SHARMA , VINAYAK HANDE , DEVARSHI MRINAL DAS . A Dynamic Comparator With Cross-Coupled Pre-Amplifier With < 160 ps Delay and 81 fJ.ns EDP[J]. Integrated Circuits and Systems, 2024 , 1(4) : 206 -213 . DOI: 10.23919/ICS.2024.3505092

References

Publishing order | Descend order by publishing year | Descend order by cited within
[1]
R. K. Siddharth, Y. Jaya Satyanarayana, Y. B. Nithin Kumar, M. H. Vasantha, and E. Bonizzoni, “A 1-V, 3-GHz strong-arm latch voltage comparator for high speed applications,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 67, no. 12, pp. 2918-2922, Dec. 2020.

[2]
H. Zhuang, W. Cao, X. Peng, and H. Tang, “A three-stage comparator and its modified version with fast speed and low kickback,” IEEE Trans. Very Large Scale Integr. Syst., vol. 29, no. 7, pp. 1485-1489, Jul. 2021.

[4]
M. Miyahara, Y. Asada, D. Paik, and A. Matsuzawa, “A low-noise self-calibrating dynamic comparator for high-speed ADCs,” in Proc. IEEE Asian Solid-State Circuits Conf., 2008, pp. 269-272.

[5]
A. Khorami and M. Sharifkhani, “A low-power high-speed comparator for precise applications,” IEEE Trans. Very Large Scale Integr. Syst., vol. 26, no. 10, pp. 2038-2049, Oct. 2018.

[6]
H. S. Bindra, C. E. Lokin, D. Schinkel, A.-J. Annema, and B. Nauta, “A 1.2-V dynamic bias latch-type comparator in 65-nm CMOS with 0.4-mV input noise,” IEEE J. Solid-State Circuits, vol. 53, no. 7, pp. 1902-1912, Jul. 2018.

[7]
S. Chevella, D. O’Hare, and I. O’Connell, “A low-power 1-V supply dynamic comparator,” IEEE Solid-State Circuits Lett., vol. 3, pp. 154-157, 2020.

[8]
K. Krishna and N. Nambath, “Cascode cross-coupled stage high-speed dynamic comparator in 65 nm CMOS,” IEEE Trans. VLSI Syst., vol. 31, no. 7, pp. 1083-1086, Jul. 2023.

[9]
J. Gao, G. Li, and Q. Li, “High-speed low-power common-mode insensitive dynamic comparator,” Electron. Lett., vol. 51, no. 2, pp. 134-136, 2015.

[10]
K. Krishna, R. Rashid, and N. Nambath, “Triple-tail common-mode insensitive high-speed dynamic comparator for analog in-memory computing architectures,” in Proc. IEEE Int. Symp. Circuits Syst., 2023, pp. 1-5.

[11]
A. Almansouri, A. Alturki, A. Alshehri, T. Al-Attar, and H. Fariborzi, “Improved Strong ARM latch comparator: Design, analysis and performance evaluation,” in Proc. 13th IEEE Conf. Ph.D. Res. Microelectron. Electron., 2017, pp. 89-92.

[12]
F. Yuan, “A comparative study of dynamic comparators in low-voltage SAR ADC,” in Proc. IEEE 67th Int. Midwest Symp. Circuits Syst., 2024, pp. 447-450.

[13]
H. Xu and A. A. Abidi, “Analysis and design of regenerative comparators for low offset and noise,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 66, no. 8, pp. 2817-2830, Aug. 2019.

[14]
S. R. Maram, S. Boyapati, and V. S. Pasupureddi, “A 1.2 v double-tail StrongARM latch comparator with 51fJ/comparison and 380 μV input noise in 65nm CMOS technology,” in Proc. 25th IEEE Int. Symp. Qual. Electron. Des., 2024, pp. 1-7.

[15]
T. Carusone, D. Johns, and K. Martin, Analog Integrated Circuit Design (Analog Integrated Circuit Design Series). Hoboken, NJ, USA: Wiley, 2011.

[16]
M. Venkatesh, G. M. Salgado, K. G. McCarthy, and I. O’Connell, “A low power programmable switch supply dynamic comparator,” in Proc. IEEE Int. Symp. Circuits Syst., 2024, pp. 1-5.

[17]
L. Qiu, T. Meng, B. Yao, Z. Du, and X. Yuan, “A high-speed low-noise comparator with auxiliary-inverter-based common mode self-regulation for low-supply-voltage SAR ADCs,” IEEE Trans. VLSI Syst., vol. 31, no. 1, pp. 152-156, Jan. 2023.

[18]
O. Aiello, P. Crovetti, P. Toledo, and M. Alioto, “Rail-to-rail dynamic voltage comparator scalable down to pW-range power and 0.15-V supply,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 68, no. 7, pp. 2675-2679, Jul. 2021.

[19]
B. Satapathy and A. Kaur, “A high speed, low energy comparator based on current recycling approach,” in Proc. IEEE Int. Symp. Circuits Syst., 2021, pp. 1-5.

[20]
H. Zhuang, C. Tong, X. Peng, and H. Tang, “Low-power, low-noise edge-race comparator for SAR ADCs,” IEEE Trans. VLSI Syst., vol. 28, no. 12, pp. 2699-2707, Dec. 2020.

[21]
X. Tang et al., “An energy-efficient comparator with dynamic floating inverter amplifier,” IEEE J. Solid-State Circuits, vol. 55, no. 4, pp. 1011-1022, Apr. 2020.

[22]
H. S. Bindra, J. Ponte, and B. Nauta,“A 174 μ VRMS input noise, 1GS/s comparator in 22 nm FDSOI with a dynamic-bias preamplifier using tail charge pump and capacitive neutralization across the latch,” in Proc. IEEE Int. Solid-State Circuits Conf., 2022, vol. 65, pp. 1-3.

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