Call for Papers

Manuscript submission deadline: Dec. 31, 2024

The advent of Large Language Models (LLMs) has revolutionized the field of artificial intelligence, driving unprecedented advancements. However, this progress brings a pressing need for high-performance and energy-efficient computing platforms. Hardware accelerators, including GPUs, CPUs, FPGAs, ASICs, and heterogeneous systems, are crucial in meeting the substantial computational demands of LLMs. Yet, the lack of effective integration between hardware and algorithms often prevents both from reaching their full potential. To achieve maximum efficiency, co-optimization of algorithms and hardware is essential. By tailoring hardware design to the specific needs of algorithms—and vice versa—significant improvements can be realized in computational throughput, energy efficiency, and overall system performance.

Addressing these challenges requires collaborative efforts from both algorithm and hardware development. On the algorithmic side, optimizations tailored to LLMs, such as pruning and quantization, are essential. Furthermore, designing or optimizing algorithms based on the characteristics of the hardware platform can enhance resource utilization, making algorithms more hardware-aware across various platforms. This calls for the urgent development of hardware-aware algorithms that maintain superior performance.

On the hardware side, optimizations for LLMs are imperative. This includes the design of specialized accelerators, energy-efficient computing paradigms, and novel memory architectures that cater to the unique demands of LLMs. Additionally, hardware architecture design must consider the deployment of algorithms across diverse platforms, optimizing resource utilization according to algorithmic characteristics to boost system performance.

This special issue aims to provide a comprehensive view of the current state and future directions of co-optimization for LLMs, emphasizing the interplay between algorithmic advancements and hardware innovations. It covers follow topics and beyond:

· Hardware/software co-design of LLMs;

· Efficient architectures for LLMs implementations;

· Computing-in-Memory accelerators for LLMs;

· Heterogeneous hardware architectures for LLMs;

· Memory optimizations for LLMs implementations;

· Algorithm optimization of LLMs considering hardware platform characteristics on GPUs, CPUs, FPGAs and ASICs;

· Hardware-aware algorithm design of LLMs;

· Efficient frameworks for LLMs deployments;

· Key Operators Optimization of LLMs;

· LLMs mapping method;

· EDA algorithm optimization of LLMs.

Submission procedure:

Prospective authors are invited to submit their papers following the instructions provided on the Integrated Circuits and Systems (ICAS) website: 

https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=10410247

The submitted manuscripts should not have been previously published, nor should they be currently under consideration for publication elsewhere. The ICAS submission site: 

https://ieee.atyponrex.com/journal/ICAS

Important dates:

Paper Submission Deadline: Dec. 31, 2024
First Round Notification: Jan. 10, 2025
Revision Submission: Feb. 15, 2025
Final Round Decision: Mar. 5, 2025
Final Submission: Mar. 20, 2025

Guest Editors:

Hao Yu, Southern University of Science and Technology, China.

Zhongfeng Wang, Sun Yat-Sen University, China.

Wei Mao, Xidian University, China.