Design-for-Test Solutions for 3-D Integrated Circuits

SHAO-CHUN HUNG, PARTHO BHOUMIK, ARJUN CHAUDHURI, SANMITRA BANERJEE, KRISHNENDU CHAKRABARTY

Integrated Circuits and Systems ›› 2024, Vol. 1 ›› Issue (1) : 3-17.

PDF(1627 KB)
PDF(1627 KB)
Integrated Circuits and Systems ›› 2024, Vol. 1 ›› Issue (1) : 3-17. DOI: 10.23919/ICS.2024.3419629
Regular Papers

Design-for-Test Solutions for 3-D Integrated Circuits

    {{javascript:window.custom_author_en_index=0;}}
  • {{article.zuoZhe_EN}}
Author information +
History +

HeighLight

{{article.keyPoints_en}}

Abstract

{{article.zhaiyao_en}}

Key words

QR code of this article

Cite this article

EndNote

Ris (Procite)

Bibtex

Download Citations
{{article.zuoZheEn_L}}. {{article.title_en}}[J]. {{journal.qiKanMingCheng_EN}}, 2024, 1(1): 3-17 https://doi.org/10.23919/ICS.2024.3419629

References

List( Publishing order | Descend order by publishing year | Descend order by cited within ) Chart analysis

References

{{article.reference}}

Funding

RIGHTS & PERMISSIONS

{{article.copyrightStatement_en}}
{{article.copyrightLicense_en}}
PDF(1627 KB)

Accesses

Citation

Detail
Sections
Recommended

/

〈 〉