PDF(2190 KB)
A 64-Gb/s 0.33-pJ/Bit PAM4 Receiver Analog Front-End With a Single-Stage Triple-Peaking CTLE Achieving 22.5-dB Boost in 40-nm CMOS Process
GUOQING WANG, ZHAO ZHANG
Integrated Circuits and Systems ›› 2024, Vol. 1 ›› Issue (2) : 103-108.
PDF(2190 KB)
PDF(2190 KB)
A 64-Gb/s 0.33-pJ/Bit PAM4 Receiver Analog Front-End With a Single-Stage Triple-Peaking CTLE Achieving 22.5-dB Boost in 40-nm CMOS Process
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