A 64-Gb/s 0.33-pJ/Bit PAM4 Receiver Analog Front-End With a Single-Stage Triple-Peaking CTLE Achieving 22.5-dB Boost in 40-nm CMOS Process

GUOQING WANG, ZHAO ZHANG

Integrated Circuits and Systems ›› 2024, Vol. 1 ›› Issue (2) : 103-108.

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Integrated Circuits and Systems ›› 2024, Vol. 1 ›› Issue (2) : 103-108. DOI: 10.23919/ICS.2024.3456043
Special Issue on Selected Papers from ICTA2023

A 64-Gb/s 0.33-pJ/Bit PAM4 Receiver Analog Front-End With a Single-Stage Triple-Peaking CTLE Achieving 22.5-dB Boost in 40-nm CMOS Process

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{{article.zuoZheEn_L}}. {{article.title_en}}[J]. {{journal.qiKanMingCheng_EN}}, 2024, 1(2): 103-108 https://doi.org/10.23919/ICS.2024.3456043

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