Regular Papers

Design-for-Test Solutions for 3-D Integrated Circuits

  • SHAO-CHUN HUNG 1 ,
  • PARTHO BHOUMIK 2 ,
  • ARJUN CHAUDHURI 3 ,
  • SANMITRA BANERJEE , 2 ,
  • KRISHNENDU CHAKRABARTY 2
Expand
  • 1 Department of Electrical and Computer Engineering, Duke University, Durham 27708 USA
  • 2 School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ 85287 USA
  • 3 NVIDIA Corporation, Santa Clara, CA 95050 USA
SANMITRA BANERJEE (e-mail: ).

PARTHO BHOUMIK, (Graduate Student Member, IEEE)

ARJUN CHAUDHURI, (Member, IEEE)

KRISHNENDU CHAKRABARTY, (Fellow, IEEE)

Received date: 2024-02-15

  Revised date: 2024-04-06

  Accepted date: 2024-05-10

  Online published: 2024-11-27

Supported by

National Science Foundation under Grant(CCF-1908045)

National Science Foundation under Grant(CCF-2309822)

Semiconductor Research Corporation (SRC) under Contract(2470)

Intel Corporation, in part by the DARPA ERI 3DSOC program under Award(HR001118C0096)

CHIMES, one of the seven centers in JUMP 2.0

DARPA through SRC Program

Abstract

As Moore’s Law approaches its limits, 3-D integrated circuits (ICs) have emerged as promising alternatives to conventional scaling methodologies. However, the benefits of 3-D integration in terms of lower power consumption, higher performance, and reduced area are accompanied by testing challenges. The unique vertical stacking of components in 3-D ICs introduces concerns related to the robustness of bonding surfaces. Moreover, immature manufacturing processes during 3-D fabrication can lead to high defect rates in different tiers. Therefore, there is a need for design-for-test solutions to ensure the reliability and performance of 3-D-integrated architectures. In this paper, we provide a comprehensive survey of existing testing strategies for 3-D ICs. We describe recent advances, including research efforts and industry practice, that address concerns related to bonding defects, elevated power supply noise, fault diagnosis, and fault localization specific to the unique characteristics of 3-D ICs.

Cite this article

SHAO-CHUN HUNG , PARTHO BHOUMIK , ARJUN CHAUDHURI , SANMITRA BANERJEE , KRISHNENDU CHAKRABARTY . Design-for-Test Solutions for 3-D Integrated Circuits[J]. Integrated Circuits and Systems, 2024 , 1(1) : 3 -17 . DOI: 10.23919/ICS.2024.3419629

[1]
W.-W. Shen and K. -N. Chen, “Three-dimensional integrated circuit (3D IC) key technology: Through-silicon via (TSV),” Nanoscale Res. Lett., vol. 12, pp. 1-9, 2017.

[2]
W. Chen and B. Bottoms, “Heterogeneous integration roadmap: Driv- ing force and enabling technology for systems of the future,” in Proc. Symp. VLSI Technol., 2019, pp. T50-T51.

[3]
J. P. Gambino, S. A. Adderly, and J. U. Knickerbocker, “An overview of through-silicon-via technology and manufacturing challenges,” Mi- croelectronic Eng., vol. 135, pp. 73-106, 2015.

[4]
J. Kim and Y. Kim, “HBM: Memory solution for bandwidth-hungry processors,” in Proc. IEEE Hot Chips Symp., 2014, pp. 1-24.

[5]
D. B. Ingerly et al., “Foveros: 3D integration and the use of face- to-face chip stacking for logic devices,” in Proc. IEEE Int. Electron Devices Meeting, 2019, pp. 19.6. 1-19.6.4.

[6]
H. Tsugawa et al., “Pixel/DRAM/logic 3-layer stacked CMOS image sensor technology,” in Proc. IEEE Int. Electron Devices Meeting, 2017, pp. 3.2. 1-3.2.4.

[7]
R. Agarwal et al., “3D packaging for heterogeneous integra- tion,” in Proc. IEEE Electron. Compon. Technol. Conf., 2022, pp. 1103-1107.

[8]
P. Batude, T. Ernst, J. Arcamone, G. Arndt, P. Coudrain, and P. Gaillardon, “3D sequential integration: A key enabling technology for heterogeneous co-integration of new function with CMOS,” IEEE Trans. Emerg. Sel. Topics Circuits Syst., vol. 2, no. 4, pp. 714-722, Dec. 2012.

[9]
S. K. Samal, K. Samadi, P. Kamal, Y. Du, and S. K. Lim, “Full chip impact study of power delivery network designs in monolithic 3D ICs,” in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., 2014, pp. 565-572.

[10]
M. Joodaki, “Uprising nano memories: Latest advances in monolithic three dimensional (3D) integrated flash memories,” Microelectronic Eng., vol. 164, pp. 75-87, 2016.

[11]
T.-T. Wu et al., “Low-cost and TSV-free monolithic 3D-IC with het- erogeneous integration of logic, memory and sensor analogy circuitry for Internet of Things,” in Proc. IEEE Int. Electron Devices Meeting, 2015, pp. 25.4. 1-25.4.4.

[12]
Y. Yu and N. K. Jha, “SPRING: A sparsity-aware reduced-precision monolithic 3D CNN accelerator architecture for training and in- ference,” IEEE Trans. Emerg. Topics Comput., vol. 10, no. 1, pp. 237-249, Jan.-Mar. 2022.

[13]
G. Murali, X. Sun, S. Yu, and S. K. Lim, “Heterogeneous mixed-signal monolithic 3-D in-memory computing using resistive RAM,” IEEE Trans. Very Large Scale Integration Syst., vol. 29, no. 2, pp. 386-396, Feb. 2021.

[14]
E. Beyne, “The 3-D interconnect technology landscape,” IEEE Des. Test, vol. 33, no. 3, pp. 8-20, Jun. 2016.

[15]
R. Lu, Y.-C. Chuang, J.-L. Wu, and J. He, “Reliability challenges from2.5D to 3DIC in advanced package development,” in Proc. IEEE Int. Rel. Phys. Symp., 2023, pp. 1-4.

[16]
T. Lu, C. Serafy, Z. Yang, S. K. Samal, S. K. Lim, and A. Sri- vastava, “TSV-based 3-D ICs: Design methods and tools,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 36, no. 10,pp. 1593-1619, Oct. 2017.

[17]
F. Laermer and A. Schilp,“Plasma polymerizing temporary etch stop,” US Patent US5,501,893, 1996.

[18]
“3D-IC platform. Web Integrity Link.” 2021. [Online] Available: https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/tools/digital-design-signoff/Integrity-3D-IC-DS-v1.pdf

[19]
“3D IC: Opportunities, challenges, and solutions.” 2021.[Online] Available:. https://semiengineering.com/3d-ic-opportunities-challenges-and-solutions/

[20]
“Shifting left for earlier testing in 2.5D and 3D IC design,” 2023.[Online] Available:. https://blogs.sw.siemens.com/semiconductor-packaging/2023/03/02/shifting-left-for-earlier-testing-in-3d-ic-design/

[21]
C.-T. Ko and K. -N. Chen, “Reliability of Key Technologies in 3D Integration,” Microelectronics Rel., vol. 53, no. 1, pp. 7-16, 2013.

[22]
P. Batude et al., “3D sequential integration: Application-driven tech- nological achievements and guidelines,” in Proc. IEEE Int. Electron Devices Meeting, 2017, pp. 3.1. 1-3.1.4.

[23]
S.-C. Hung, Y.-C. Lu, S. K. Lim, and K. Chakrabarty, “Power supply noise-aware at-speed delay fault testing of monolithic 3-D ICs,” IEEE Trans. Very Large Scale Integr. Syst., vol. 29, no. 11, pp. 1875-1888, Nov. 2021.

[24]
L. Brunet et al., “Breakthroughs in 3D sequential technology,” in Proc. IEEE Int. Electron Devices Meeting, 2018, pp. 7.2. 1-7.2.4.

[25]
S. Panth, K. Samadi, Y. Du, and S. K. Lim, “Design and cad methodologies for low power gate-level monolithic 3D ICs,” in Proc. IEEE/ACM Int. Symp. Low Power Electron. Des., 2014, pp. 171-176.

[26]
B. W. Ku, K. Chang, and S. K. Lim, “Compact-2D: A physical de- sign methodology to build commercial-quality face-to-face-bonded 3D ICs,” in Proc. Int. Symp. Phys. Des., 2018, pp. 90-97.

[27]
Y.-C. Lu, S. Pentapati, L. Zhu, K. Samadi, and S. K. Lim, “TP-GNN: A graph neural network framework for tier partitioning in monolithic 3D ICs,” in Proc. ACM/IEEE Des. Automat. Conf., 2020, pp. 1-6.

[28]
M. Raghu and E. Schmidt, “A survey of deep learning for scientific discovery,” 2020, arXiv:2003.11755.

[29]
M. M. Waldrop, “The chips are down for Moore’s law,” Nature News, vol. 530, no. 7589, 2016, Art. no. 144.

[30]
D. Ivanovich, C. Zhao, X. Zhang, R. D. Chamberlain, A. Deliwala, and V. Gruev, “Chip-to-chip optical data communications using polar- ization division multiplexing,” in Proc. IEEE High Perform. Extreme Comput. Conf., 2020, pp. 1-8.

[31]
P. Ambs, “Optical computing: A 60-year adventure,” Adv. Opt. Tech- nol., vol. 2010, no. 1, 2010, Art. no. 372652.

[32]
R. A. Athale and W. C. Collins, “Optical matrix-matrix multiplier based on outer product decomposition,” Appl. Opt., vol. 21, no. 12,pp. 2089-2090, 1982.

[33]
L. Chrostowski and M. Hochberg. Silicon Photonics Design: From Devices to Systems. Cambridge, U.K.: Cambridge University Press, 2015.

[34]
Y. Zhang, A. Samanta, K. Shang, and S. J. B. Yoo, “Scalable 3D silicon photonic electronic integrated circuits and their applications,” IEEE J. Sel. Topics Quantum Electron., vol. 26, no. 2, Mar./Apr. 2020,Art. no. 8201510.

[35]
K. Shang, S. Pathak, B. Guan, G. Liu, and S. J. B. Yoo, “Low-loss compact multilayer silicon nitride platform for 3D photonic integrated circuits,” Opt. Exp., vol. 23, no. 16, pp. 21334-21342, 2015.

[36]
Y. Zhang, Y.-C. Ling, Y. Zhang, K. Shang, and S. J. B. Yoo, “High- density wafer-scale 3-D silicon-photonic integrated circuits,” IEEE J. Sel. Topics Quantum Electron., vol. 24, no. 6, Nov./Dec. 2018, Art no. 8200510.

[37]
S. Banerjee, M. Nikdast, and K. Chakrabarty, “Modeling silicon- photonic neural networks under uncertainties,” in Proc. Des. Automat. Test Europe Conf. Exhib., 2021, pp. 98-101.

[38]
S. Banerjee, M. Nikdast, and K. Chakrabarty, “On the impact of uncer- tainties in silicon-photonic neural networks,” IEEE Des. Test Comput., vol. 40, no. 2, pp. 82-89, Apr. 2023.

[39]
S. Banerjee, M. Nikdast, and K. Chakrabarty, “Characteriz- ing coherent integrated photonic neural networks under imper- fections,” J. Lightw. Technol., vol. 41, no. 5, pp. 1464-1479, Mar. 2023.

[40]
A. Shafiee, S. Banerjee, K. Chakrabarty, S. Pasricha, and M. Nikdast, “LOCI: An analysis of the impact of optical loss and crosstalk noise in integrated silicon-photonic neural networks,” in Proc. Great Lakes Symp., 2022, pp. 351-355.

[41]
S. Banerjee, M. Nikdast, S. Pasricha, and K. Chakrabarty, “Champ: Coherent hardware-aware magnitude pruning of integrated photonic neural networks,” in Proc. Opt. Fiber Commun. Conf. Exhib., 2022, Paper M2G.3.

[42]
S. Banerjee, M. Nikdast, S. Pasricha, and K. Chakrabarty, “Pruning coherent integrated photonic neural networks using the lottery ticket hypothesis,” in Proc. IEEE Comput. Soc. Annu. Symp. VLSI, 2022,pp.128-133.

[43]
E. J. Marinissen, “Testing TSV-based three-dimensional stacked ICs,” in Proc. Des. Automat. Test Europe Conf. Exhib., 2010, pp. 1689-1694.

[44]
K. Chakrabarty, S. Deutsch, H. Thapliyal, and F. Ye, “TSV de- fects and TSV-induced circuit failures: The third dimension in test and design-for-test,” in Proc. IEEE Int. Rel. Phys. Symp., 2012,pp.5F. 1.1-5F.1.12.

[45]
K. Xu, Y. Yu, and X. Fang, “The detection of open and leakage faults for prebond TSV test based on weak current source,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 41, no. 9,pp. 2768-2779, Sep. 2022.

[46]
B. Noia and K. Chakrabarty, “Pre-bond probing of through-silicon vias in 3-D stacked ICs,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 32, no. 4, pp. 547-558, Apr. 2013.

[47]
D. K. Maity, S. K. Roy, and C. Giri,“Identification of faulty TSVs in 3D IC during pre-bond testing,” in Proc. 31st Int. Conf. VLSI Des. 17th Int. Conf. Embedded Syst., 2018, pp. 109-114.

[48]
B. Zhang and V. Agrawal,“An optimal probing method of pre- bond TSV fault identification in 3D stacked ICs,” in Proc. SOI- 3D-Subthreshold Microelectronics Technol. Unified Conf., 2014,pp.1-3.

[49]
B. Zhang and V. D. Agrawal, “Diagnostic tests for pre-bond TSV defects,” in Proc. 28th Int. Conf. VLSI Des., 2015, pp. 387-392.

[50]
D. K. Maity, S. K. Roy, and C. Giri, “Identification of ran- dom/clustered TSV defects in 3D IC during pre-bond testing,” J. Electron. Testing, vol. 35, pp. 741-759, 2019.

[51]
S. Deutsch and K. Chakrabarty, “Non-invasive pre-bond TSV test us- ing ring oscillators and multiple voltage levels,” in Proc. Des. Automat. Test Europe Conf. Exhib., 2013, pp. 1065-1070.

[52]
Y. Fkih, P. Vivet, B. Rouzeyre, M.-L. Flottes, and G. Di Natale,“A 3D IC BIST for pre-bond test of TSVs using ring oscillators,” in Proc. IEEE 11th Int. New Circuits Syst. Conf., 2013, pp. 1-4.

[53]
N. Georgoulopoulos and A. Hatzopoulos, “Effectiveness evaluation of the TSV fault detection method using ring oscillators,” in Proc. 6th Int. Conf. Modern Circuits Syst. Technol., 2017, pp. 1-4.

[54]
H. Chang and H. Liang,“Pulse shrinkage based pre-bond through silicon vias test in 3D IC,” in Proc. IEEE 33rd VLSI Test Symp., 2015,pp.1-6.

[55]
M. Yi, J. Bian, T. Ni, C. Jiang, H. Chang, and H. Liang, “A pulse shrinking-based test solution for prebond through silicon via in 3-D ICs,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 38, no. 4, pp. 755-766, Apr. 2019.

[56]
S. M. Menon and R. R. Roeder, “No-touch stress testing of memory i/o interfaces,” U.S. Patent 8, 924,786 B2. Dec. 30, 2014.

[57]
S. Das, F. Su, and S. Chakravarty, “A PVT-resilient no-touch DFT methodology for prebond TSV testing,” in Proc. IEEE Int. Test Conf., 2018, pp. 1-10.

[58]
D. Arumí, R. Rodríguez-Montañés, and J. Figueras, “Prebond testing of weak defects in TSVs,” IEEE Trans. Very Large Scale Integr. Syst., vol. 24, no. 4, pp. 1503-1514, Apr. 2016.

[59]
E. J. Marinissen, “Challenges in testing TSV-based 3D stacked ICs: Test flows, test contents, and test access,” in Proc. IEEE Asia Pacific Conf. Circuits Syst., 2010, pp. 544-547.

[60]
Y.-J. Huang, J.-F. Li, J.-J. Chen, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu,“A built-in self-test scheme for the post-bond test of TSVs in 3D ICs,” in Proc. 29th VLSI Test Symp., 2011, pp. 20-25.

[61]
D. Maity, S. Roy, C. Giri, and H. Rahaman, “Identification of faulty TSV with a built-in self-test mechanism,” in Proc. IEEE 27th Asian Test Symp., 2018, pp. 1-6.

[62]
D. K. Maity, S. K. Roy, and C. Giri, “Built-in self-repair for manu- facturing and runtime TSV defects in 3D ICs,” in Proc. IEEE Int. Test Conf. India, 2020, pp. 1-6.

[63]
M. Cho, C. Liu, D. H. Kim, S. K. Lim, and S. Mukhopadhyay, “Pre-bond and post-bond test and signal recovery structure to char- acterize and repair TSV defect induced signal degradation in 3-D system,” IEEE Trans. Compon. Packag. Manuf. Technol., vol. 1, no. 11, pp. 1718-1727, Nov. 2011.

[64]
F. Ye and K. Chakrabarty,“TSV open defects in 3D integrated circuits: Characterization, test, and optimal spare allocation,” in Proc. 49th Annu. Des. Automat. Conf., 2012, pp. 1024-1030.

[65]
H. Sung, K. Cho, K. Yoon, and S. Kang, “A delay test architec- ture for TSV with resistive open defects in 3-D stacked memories,” IEEE Trans. Very Large Scale Integration Syst., vol. 22, no. 11,pp. 2380-2387, Nov. 2014.

[66]
Y.-W. Lee, H. Lim, and S. Kang, “Grouping-based TSV test ar- chitecture for resistive open and bridge defects in 3-D-ICs,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 36, no. 10,pp. 1759-1763, Oct. 2017.

[67]
S.-G. Papadopoulos, V. Gerakis, Y. Tsiatouhas, and A. Hatzopoulos, “Oscillation-based technique for post-bond parallel testing and diag- nosis of multiple TSVs,” in Proc. 27th Int. Symp. Power Timing Model. Optim. Simul., 2017, pp. 1-6.

[68]
R. Rodríguez-Montañés, D. Arumí, and J. Figueras, “Postbond test of through-silicon vias with resistive open defects,” IEEE Trans. Very Large Scale Integration. Syst., vol. 27, no. 11, pp. 2596-2607, Nov. 2019.

[69]
Y. Yu, X. Fang, and X. Peng, “A post-bond TSV test method based on RGC parameters measurement,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 39, no. 2, pp. 506-519, Feb. 2020.

[70]
W.-H. Lo, K. Chi, and T. Hwang, “Architecture of ring-based redun- dant TSV for clustered faults,” IEEE Trans. Very Large Scale Integr. Syst., vol. 24, no. 12, pp. 3437-3449, Dec. 2016.

[71]
L. Jiang, Q. Xu, and B. Eklow, “On effective through-silicon via repair for 3-D-stacked ICs,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 32, no. 4, pp. 559-571, Apr. 2013.

[72]
I. Lee, M. Cheong, and S. Kang, “Highly reliable redundant TSV architecture for clustered faults,” IEEE Trans. Rel., vol. 68, no. 1,pp. 237-247, Mar. 2019.

[73]
T. Ni, D. Liu, Q. Xu, Z. Huang, H. Liang, and A. Yan, “Architecture of cobweb-based redundant TSV for clustered faults,” IEEE Trans. Very Large Scale Integration Syst., vol. 28, no. 7, pp. 1736-1739, Jul. 2020.

[74]
T. Ni et al., “LCHR-TSV: Novel low cost and highly repairable honeycomb-based TSV redundancy architecture for clustered faults,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 39, no. 10,pp. 2938-2951, Oct. 2020.

[75]
IEEE Standard for Test Access Port and Boundary-Scan Architecture, IEEE Standard 1149.1TM- 2013, 2013.

[76]
IEEE, IEEE Standard Testability Method for Embedded Core- Based Integrated Circuits, IEEE Standard 1500TM- 2005, 2005, doi: 10.1109/IEEESTD.2005.96290.

[77]
E. J. Marinissen, T. McLaurin, and H. Jiao,“IEEE std P1838: DfT standard-under-development for 2.5D-, 3D-, and 5.5D-SICs,” in Proc. 21th IEEE Eur. test Symp., 2016, pp. 1-10.

[78]
A. Cron and E. J. Marinissen,“IEEE standard 1838 is on the move,”Computer, vol. 54, no. 11, pp. 88-94, 2021.

[79]
J. Michel, J. Liu, and L. C. Kimerling, “High-performance Ge-on-Si photodetectors,” Nature Photon., vol. 4, no. 8, pp. 527-534, 2010.

[80]
J. De Coster et al., “Test-station for flexible semi-automatic wafer- level silicon photonics testing,” in Proc. IEEE Eur. Test Symp., 2016,pp.1-6.

[81]
V. Grimaldi, F. Zanetto, F. Toso, C. De Vita, and G. Ferrari,“Non- invasive light sensor with enhanced sensitivity for photonic integrated circuits,” in Proc. 17th Conf. Ph. D. Res. Microelectron. Electron., 2022, pp. 285-288.

[82]
F. Morichetti et al., “Non-invasive on-chip light observation by con- tactless waveguide conductivity monitoring,” IEEE J. Sel. Topics Quantum Electron., vol. 20, no. 4, Jul./Aug. 2014, Art. no. 8201710.

[83]
K. Chang, S. Das, S. Sinha, B. Cline, G. Yeric, and S. K. Lim, “System-level power delivery network analysis and optimization for monolithic 3D ICs,” IEEE Trans. Very Large Scale Integration Syst., vol. 27, no. 4, pp. 888-898, Apr. 2019.

[84]
A. Koneru, A. Todri-Sanial, and K. Chakrabarty, “Reliable power de- livery and analysis of power-supply noise during testing in monolithic 3D ICs,” in Proc. IEEE VLSI Test Symp., 2019, pp. 1-6.

[85]
S.-C. Hung and K. Chakrabarty, “Design of a reliable power delivery network for monolithic 3D ICs,” in Proc. Des. Automat. Test Europe Conf. Exhib., 2020, pp. 1746-1751.

[86]
S.-C. Hung, Y.-C. Lu, S. K. Lim, and K. Chakrabarty, “Power supply noise-aware scan test pattern reshaping for at-speed delay fault testing of monolithic 3D ICs,” in Proc. IEEE Asian Test Symp., 2020, pp. 1-6.

[87]
S.-C. Hung, A. Chaudhuri, S. Banerjee, and K. Chakrabarty, “Fault diagnosis for resistive random-access memory and monolithic inter- tier vias in monolithic 3D integration,” in Proc. IEEE Int. Test Conf., 2022, pp. 118-127.

[88]
S.-C. Hung, A. Chaudhuri, and K. Chakrabarty, “Test-point insertion for power-safe testing of monolithic 3D ICs using reinforcement learn- ing,” in Proc. IEEE Eur. Test Symp., 2023, pp. 1-6.

[89]
S.-C. Hung, A. Chaudhuri, S. Banerjee, and K. Chakrabarty, “Scan cell segmentation based on reinforcement learning for power-safe testing of monolithic 3D ICs,” in Proc. IEEE Int. Test Conf., 2023, pp. 216-225.

[90]
C. Xu, D. Niu, Y. Zheng, S. Yu, and Y. Xie, “Impact of cell failure on reliable cross-point resistive memory design,” ACM Trans. Des. Automat. Electron. Syst., vol. 20, no. 4, pp. 1-21, 2015.

[91]
E. Esmanhotto et al., “High-density 3D monolithically integrated mul- tiple 1T1R multi-level-cell for neural networks,” in Proc. IEEE Int. Electron Devices Meeting, 2020, pp. 36.5. 1-36.5.4.

[92]
Z. Jiang, S. Yu, Y. Wu, J. H. Engel, X. Guan, and H.-S. P. Wong, “Verilog-A compact model for oxide-based resistive random access memory (RRAM),” in Proc. Int. Conf. Simul. Semicond. Processes Devices, 2014, pp. 41-44.

[93]
A. Chaudhuri, S. Banerjee, J. Kim, S. Lim, and K. Chakrabarty, “Built- in self-test of high-density and realistic ILV layouts in monolithic 3-D ICs,” IEEE Trans. Very Large Scale Integration. Syst., vol. 31, no. 3,pp. 296-309, Mar. 2023.

[94]
A. Chaudhuri, S. Banerjee, H. Park, B. W. Ku, K. Chakrabarty, and S.-K. Lim, “Built-in self-test for inter-layer vias in monolithic 3D ICs,” in Proc. IEEE Eur. Test Symp., 2019, pp. 1-6.

[95]
A. Mallik et al., “The impact of sequential-3D integration on semicon- ductor scaling roadmap,” in Proc. IEEE Int. Electron Devices Meeting, 2017, pp. 32.1. 1-31.1.4.

[96]
A. Koneru, S. Kannan, and K. Chakrabarty, “Impact of electrostatic coupling and wafer-bonding defects on delay testing of monolithic 3D integrated circuits,” ACM J. Emerg. Technol. Comput. Syst., vol. 13, no. 4, pp. 1-23, 2017.

[97]
S.-C. Hung, S. Banerjee, A. Chaudhuri, J. Kim, S. K. Lim, and K. Chakrabarty, “Transferable graph neural network-based delay-fault localization for monolithic 3-D ICs,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 42, no. 11, pp. 4296-4309, Nov. 2023.

[98]
S.-C. Hung, S. Banerjee, A. Chaudhuri, and K. Chakrabarty, “Graph neural network-based delay-fault localization for monolithic 3D ICs,” in Proc. Des. Automat. Test Europe Conf. Exhib., 2022, pp. 448-453.

[99]
A. Chaudhuri, S. Banerjee, and K. Chakrabarty, “NodeRank: Observation-point insertion for fault localization in monolithic 3D ICs,” in Proc. IEEE Asian Test Symp., 2020, pp. 1-6.

[100]
J. H. Lau,“3D IC integration and 3D IC packaging,” in Semiconductor Advanced Packaging, Berlin, Germany: Springer, 2021, pp. 343-378.

[101]
“Test automation of 3D integrated systems.” 2012.[Online] Available:. https://api.semanticscholar.org/CorpusID:259654823

[102]
“Tessent multidie Web Link.” 2022. [Online] Available: https://static.sw.cdn.siemens.com/siemens-disw-assets/public/5VeJ6OifkuLPXkZIfiNFMK/en-US/Siemens-SW-Tessent-multi-die-FS-84857-C2.pdf

[103]
“ATE Solutions to 3D-IC Test Challenges.” [Online] Available:. https://www3.advantest.com/documents/11348/6f2b1d79-526e-4637-8ba8-9b746bd49618

[104]
“TSMC 3DFabricTM alliance.” [Online] Available:. https://www.tsmc.com/english/dedicatedFoundry/oip/3dfabric_alliance

Outlines

/