Integrated Circuits and Systems >

2024 , Vol. 1 >Issue 1: 3 - 17

DOI: https://doi.org/10.23919/ICS.2024.3419629

Regular Papers

Design-for-Test Solutions for 3-D Integrated Circuits

  • SHAO-CHUN HUNG 1 ,
  • PARTHO BHOUMIK 2 ,
  • ARJUN CHAUDHURI 3 ,
  • SANMITRA BANERJEE , 2 ,
  • KRISHNENDU CHAKRABARTY 2
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  • 1 Department of Electrical and Computer Engineering, Duke University, Durham 27708 USA
  • 2 School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ 85287 USA
  • 3 NVIDIA Corporation, Santa Clara, CA 95050 USA
SANMITRA BANERJEE (e-mail: ).

PARTHO BHOUMIK, (Graduate Student Member, IEEE)

ARJUN CHAUDHURI, (Member, IEEE)

KRISHNENDU CHAKRABARTY, (Fellow, IEEE)

Received date: 2024-02-15

  Revised date: 2024-04-06

  Accepted date: 2024-05-10

  Online published: 2024-11-27

Supported by

National Science Foundation under Grant(CCF-1908045)

National Science Foundation under Grant(CCF-2309822)

Semiconductor Research Corporation (SRC) under Contract(2470)

Intel Corporation, in part by the DARPA ERI 3DSOC program under Award(HR001118C0096)

CHIMES, one of the seven centers in JUMP 2.0

DARPA through SRC Program

Fold

Abstract

As Moore’s Law approaches its limits, 3-D integrated circuits (ICs) have emerged as promising alternatives to conventional scaling methodologies. However, the benefits of 3-D integration in terms of lower power consumption, higher performance, and reduced area are accompanied by testing challenges. The unique vertical stacking of components in 3-D ICs introduces concerns related to the robustness of bonding surfaces. Moreover, immature manufacturing processes during 3-D fabrication can lead to high defect rates in different tiers. Therefore, there is a need for design-for-test solutions to ensure the reliability and performance of 3-D-integrated architectures. In this paper, we provide a comprehensive survey of existing testing strategies for 3-D ICs. We describe recent advances, including research efforts and industry practice, that address concerns related to bonding defects, elevated power supply noise, fault diagnosis, and fault localization specific to the unique characteristics of 3-D ICs.

Key words： 3-D integrated circuits; design for test; through-silicon vias

Cite this article

SHAO-CHUN HUNG , PARTHO BHOUMIK , ARJUN CHAUDHURI , SANMITRA BANERJEE , KRISHNENDU CHAKRABARTY . Design-for-Test Solutions for 3-D Integrated Circuits[J]. Integrated Circuits and Systems, 2024 , 1(1) : 3 -17 . DOI: 10.23919/ICS.2024.3419629

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