Integrated Circuits and Systems >

2024 , Vol. 1 >Issue 2: 103 - 108

DOI: https://doi.org/10.23919/ICS.2024.3456043

Special Issue on Selected Papers from ICTA2023

A 64-Gb/s 0.33-pJ/Bit PAM4 Receiver Analog Front-End With a Single-Stage Triple-Peaking CTLE Achieving 22.5-dB Boost in 40-nm CMOS Process

  • GUOQING WANG 1 ,
  • ZHAO ZHANG , 1, 2
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  • 1 Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100084, China
  • 2 University of Chinese Academy of Sciences, Beijing 101408, China
Zhao Zhang (e-mail: ).

Received date: 2024-03-22

  Revised date: 2024-07-23

  Accepted date: 2024-08-20

  Online published: 2024-11-27

Supported by

National Natural Science Foundation of China under Grant 62222409 and Grant(62174153)

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Abstract

This work presents a PAM4 receiver analog frontend (AFE) operating up to 64 Gb/s. The electronic integrated circuit (EIC) is fabricated in 40-nm CMOS technology. This AFE is composed of a single-stage Continuous-Time Linear Equalizer (CTLE), a Variable Gain Amplifier (VGA), an input impedance matching network, a buffer stage, and an output buffer. The single-stage triple-peaking CTLE proposed employs current reuse technique and a multi-feedback structure, enabling the adjustment of peaking in the low, mid, and high-frequency bands. Thus, only one-stage CTLE is sufficient to achieve an over-20-dB boost at Nyquist frequency to save power. The VGA adopts an enhanced structure based on the Gilbert cell, where the gain is manipulated by controlling the gate voltage of MOS transistors. The CTLE undergoes variations in its DC gain during the adjustment process to equalize channel losses. The role of the VGA is to stable the DC gain changes induced by the adjustment of the CTLE. The output buffer adopts two stages, aiming to ensure that the gain does not attenuate excessively while maintaining output impedance matching. The AFE consumes 21.1 mW with a supply voltage of 1.5/1 V. It can provide a maximum boost of 22.5 dB, and the data rate reaches up to 64 Gb/s. Additionally, it features peaking adjustment capabilities in the low, mid, and high-frequency bands. Finally, the measurement demonstrates its ability to effectively equalize a channel with a 12-dB loss at the Nyquist frequency of 16 GHz.

Key words： Analog front-end (AFE); continuous-time linear equalizer (CTLE); VGA; triple peaking; PAM4; low-power

Cite this article

GUOQING WANG , ZHAO ZHANG . A 64-Gb/s 0.33-pJ/Bit PAM4 Receiver Analog Front-End With a Single-Stage Triple-Peaking CTLE Achieving 22.5-dB Boost in 40-nm CMOS Process[J]. Integrated Circuits and Systems, 2024 , 1(2) : 103 -108 . DOI: 10.23919/ICS.2024.3456043

References

Publishing order | Descend order by publishing year | Descend order by cited within
[1]
Y. Frans et al. , “A 56-Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16-nm FinFET,” IEEE J. Solid-State Circuits, vol. 52, no. 4, pp. 1101- 1110, Apr. 2017.

[2]
J. Lee, P.-C. Chiang, P.-J. Peng, L.-Y. Chen, and C.-C. Weng, “Design of 56 Gb/s NRZ and PAM4 SerDes transceivers in CMOS technologies,” IEEE J. Solid-State Circuits, vol. 50, no. 9, pp. 2061- 2073, Sep. 2015.

[3]
J. Im et al. , “A 112-Gb/s PAM-4 long-reach wireline transceiver using a 36-way time-interleaved SAR ADC and inverter-based RX analog front-end in 7-nm FinFET,” IEEE J. Solid-State Circuits, vol. 56, no. 1, pp. 7- 18, Jan. 2021.

[4]
J. Bailey et al. , “A 112-Gb/s PAM-4 low-power nine-tap sliding-block DFE in a 7-nm FinFET wireline receiver,” IEEE J. Solid-State Circuits, vol. 57, no. 1, pp. 32- 43, Jan. 2022.

[5]
E. Depaoli et al. , “A 64 Gb/s low-power transceiver for short-reach PAM-4 electrical links in 28-nm FDSOI CMOS,” IEEE J. Solid-State Circuits, vol. 54, no. 1, pp. 6- 17, Jan. 2019.

[6]
K. Zheng et al. , “An inverter-based analog front end for a 56 GB/S PAM4 wireline transceiver in 16NMCMOS,” in 2018 IEEE Symp. VLSI Circuits , Honolulu, HI, USA, 2018, pp. 269- 270.

[7]
G. Wang et al. , “A 64-Gb/s 0.33-pJ/bit PAM4 receiver analog front-end with a single-stage triple-peaking CTLE achieving 22.5-dB boost in 40- nm CMOS process,” in 2023 IEEE Int. Conf. Integr. Circuits, Technol. Appl. Hefei, China, 2023, pp. 120- 121.

[8]
Y. Krupnik et al. , “112-Gb/s PAM4 ADC-based SERDES receiver with resonant AFE for long-reach channels,” IEEE J. Solid-State Circuits, vol. 55, no. 4, pp. 1077- 1085, Apr. 2020.

[9]
S. Parikh et al. , “A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS,” in 2013 IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers San Francisco, CA, USA, 2013, pp. 28- 29.

[10]
A. Atharav and B. Razavi, “A 56-Gb/s 50-mW NRZ receiver in 28- nm CMOS,” IEEE J. Solid-State Circuits, vol. 57, no. 1, pp. 54- 67, Jan. 2022.

[11]
B. Ye et al. , “A 2.29-pJ/b 112-Gb/s wireline transceiver with RX four- tap FFE for medium-reach applications in 28-nm CMOS,” IEEE J. Solid-State Circuits, vol. 58, no. 1, pp. 19- 29, Jan. 2023.

[12]
H. Lin et al. , “ADC-DSP-based 10-to-112-Gb/s multi-standard re- ceiver in 7-nm FinFET,” IEEE J. Solid-State Circuits, vol. 56, no. 4, pp. 1265- 1277, Apr. 2021.

[13]
Z. Li, M. Tang, T. Fan, and Q. Pan, “A 56-Gb/s PAM4 receiver ana- log front-end with fixed peaking frequency and bandwidth in 40-nm CMOS,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 68, no. 9, pp. 3058- 3062, Sep. 2021.

[14]
I. Petricli, H. Zhang, E. Monaco, G. Albasini, and A. Mazzanti, “A 112 Gb/s PAM-4 RX front-end with unclocked decision feedback equalizer,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 68, no. 1, pp. 256- 260, Jan. 2021.

[15]
D. Wang et al. , “A 56-Gbps PAM-4 wireline receiver with 4-tap direct DFE employing dynamic CML comparators in 65 nm CMOS,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 69, no. 3, pp. 1027- 1040, Mar. 2022.

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