Integrated Circuits and Systems >

2024 , Vol. 1 >Issue 2: 109 - 118

DOI: https://doi.org/10.23919/ICS.2024.3423852

Special Issue on Selected Papers from ICTA2023

A 312.5 Mbps-32 Gbps JESD204C Wireline Transceiver Back-Compatible With JESD204B in 28 nm CMOS

  • SHIJIE LI ,
  • RUICHANG MA ,
  • MINGXING DENG ,
  • JIAMIN XUE ,
  • WEI DENG ,
  • BAOYONG CHI ,
  • HAIKUN JIA
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  • Tsinghua University, Beijing 100000, China

SHIJIE LI received the B.S. degree in electronic science and technology from Tianjin University, Tianjin, China, in 2019. He is currently a third- year postgraduate with the School of Integrated Circuits, Tsinghua University, Beijing, China. His research interests include the field of high-speed serial interface system and circuits.

RUICHANG MA (Student Member, IEEE) re- ceived the B.S. degree from Sichuan University, Sichuan, China, in 2017, and the M.S. degree in 2020, from Tsinghua University, Beijing, China, where he is currently working toward the Ph.D. degree with the School of Integrated Circuits. His research interests include high-performance clock generation and system design for demodulation of digital baseband.

MINGXING DENG received the B.S. degree from the School of Electronic Science and Engineering, University of Electronic Science and Technology of China, Chengdu, China, in 2019, and the M.S. degree from the Institute of Microelectronics, Ts- inghua University, Beijing, China, in 2022. His research interests include the circuit design of wireless and high speed wireline receivers.

JIAMIN XUE received the B.S. degree from the School of Microelectronics, Xidian University, Xi’an, China, in 2019, and the M.S. degree from the Institute of Microelectronics, Tsinghua Univer- sity, Beijing, China, in 2022. His research interests include the circuit design of wireless transceivers and high speed interfaces.

WEI DENG (Senior Member, IEEE) received the B.S. and M.S. degrees in electronic engineering from the University of Electronic Science and Technology of China (UESTC), Chengdu, China, in 2006 and 2009, respectively, and the Ph.D. degree in electronic engineering from the Tokyo Institute of Technology, Tokyo, Japan, in 2013. From 2013 to 2014, he was a Postdoctoral Re- searcher with the Tokyo Institute of Technology. From 2015 to 2019, he was with Apple Inc., Cu- pertino, CA, USA, working on radio frequency (RF), millimeter-wave (mm-wave), and mixed-signal IC design for wireless transceivers and Apple A-series processors. Since 2019, he has been with the School of Integrated Circuits, Tsinghua University, Beijing, China, where he is currently an Associate Professor. He has authored or coauthored more than 120 IEEE journal articles and conference papers. His research inter- ests include RF, mm-wave, terahertz, and mixed-signal integrated circuits and systems for wireless communications, radars, and imaging systems. Dr. Deng is a Technical Program Committee (TPC) Member of the IEEE Inter- national Solid-State Circuits Conference (ISSCC), IEEE VLSI Symposium on Technology and Circuits (VLSI), and IEEE European SolidState Circuits Conference (ESSCIRC). He was the recipient of several national and international awards, including the China Youth Science and Technology Innovation Award, IEEE SSCS Predoctoral Achievement Award, Chinese Government Award for Outstanding Self-Financed (non-government sponsored) Students Abroad, Tejima Research Award, and IEEE/ACM ASP-DAC Best Design Award. He has been an Associate Editor for IEEE SOLID-STATE CIRCUITS LETTERS.

BAOYONG CHI (Senior Member, IEEE) received the B.S. degree in microelectronics from Peking University, Beijing, China, in 1998, and the Ph.D. degree from Tsinghua University, Beijing, in 2003. From 2006 to 2007, he was a Visiting Assistant Professor with Stanford University, Stanford, CA, USA. He is currently a Full Professor and the Deputy Director of the Institute of Microelectron- ics, Tsinghua University. He has authored more than 140 academic articles and two books, and holds more than 20 patents. His research interests include RF/millimeter-wave integrated circuit design, analog integrated circuit design, and monolithic wireless transceiver chips for radar and communication. Dr. Chi has been a TPC Member of A-SSCC since 2005.

HAIKUN JIA (Member, IEEE) received the B.S. and Ph.D. degrees in electronics engineering from Tsinghua University, Beijing, China, in 2009 and 2015, respectively. He is currently an Assistant Professor with the School of Integrated Circuits, Tsinghua University. His research interests include the field of millimeter-wave and high-speed circuit and system design, including power amplifier (PA), voltage-controlled oscillator (VCO), and frequency modulated continuous wave (FMCW) radar.

Received date: 2024-02-27

  Revised date: 2024-04-26

  Accepted date: 2024-05-14

  Online published: 2024-11-27

Supported by

Beijing Municipal Science and Technology through Project Number(Z221100007722024)

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Abstract

This paper presents a 32 Gbps wireline transceiver that not only supports the JESD204 C standard but also maintains back-compatibility with JESD204B with minimal additional circuitry. Additionally, a pattern-filtered phase detector (PFPD) is proposed to circumvent the side effect of ambiguous sampling clock phase caused by loop-unrolled 1st post-cursor tap equalization scheme in the decision-feedback equalization (DFE). A 16 GHz external half-rate clock is injected into an on-chip injection-locked ring oscillator to distribute the 16 GHz clock for both the receiver and the transmitter. Multiple on-chip adaption engines and calibration loops are also added to assist the whole system work properly, such as tap weight and desired level adaption engine integrated into the decision-feedback equalizer, duty cycle distortion correction and IQ-mismatch correction. Fabricated in 28 nm CMOS process, the proposed transceiver demonstrates its ability to operate within a signaling range from 312.5 Mbps to 32 Gbps, achieving a BER below 10−12 over a 14.9 dB channel loss at Nyquist frequency. It occupies an aggregated area of 1.4 mm2 and consumes 203 mW at 32 Gbps, in which 50 mW for the transmitter (TX) and 153 mW for the receiver (RX), therefore end up achieving 6.34pJ/bit power efficiency at 32 Gbps.

Key words： Clock and data recovery (CDR); decision-feedback equalization; JESD204 C; phase detector; wireline transceiver

Cite this article

SHIJIE LI , RUICHANG MA , MINGXING DENG , JIAMIN XUE , WEI DENG , BAOYONG CHI , HAIKUN JIA . A 312.5 Mbps-32 Gbps JESD204C Wireline Transceiver Back-Compatible With JESD204B in 28 nm CMOS[J]. Integrated Circuits and Systems, 2024 , 1(2) : 109 -118 . DOI: 10.23919/ICS.2024.3423852

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