Integrated Circuits and Systems >

2025 , Vol. 2 >Issue 1: 4 - 12

DOI: https://doi.org/10.23919/ICS.2025.3553460

Special Issue Papers

Edge-Optimized AI Architecture: MRAM-Based Near Memory Computing Macro Balancing Between Memory Capacity and Computation

  • XI YANG 1 ,
  • YAMIN MAO 2 ,
  • LIANG CHANG , 1, 3 ,
  • HAOJIE WEI 1 ,
  • YUANBO WANG 1 ,
  • JINGKE WANG 1 ,
  • CHAO FAN 4 ,
  • ZHONGMOU WU 3 ,
  • SHOUZHONG PENG 5 ,
  • JUN ZHOU 1
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  • 1 School of Information and Communication Engineering, University of Electronic Science and Technology of China, Chengdu 611731, China
  • 2 CETC Rongwei Electronic Technology Company, Ltd., Chengdu 610036, China
  • 3 Casicyber Industrial Technology Research Institute, Chengdu 610317, China
  • 4 Beijing Houmo AI Inc., Beijing 100176, China
  • 5 Anhui Province Key Laboratory of Spintronic Chip Research and Manufacturing, Hefei Innovation Research Institute, Beihang University, Hefei 230013, China
LIANG CHANG (e-mail: ).

XI YANG (Student Member, IEEE)；

LIANG CHANG(Member, IEEE)；

SHOUZHONG PENG(Member, IEEE)；

JUN ZHOU (Senior Member, IEEE)

Received date: 2025-01-10

  Revised date: 2025-03-11

  Accepted date: 2025-03-16

  Online published: 2025-10-22

Supported by

Open Project Program of Anhui Province Key Laboratory of Spintronic Chip Research and Manufacturing under Grant WNKFKT-25-01, in part by the National Science Foundation of China under Grant 62104025, and in part by the State Key Laboratory of Computer Architecture (ICT, CAS) under Grant CLQ202305

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Abstract

General-purpose edge neural networks need a lightweight architecture that effectively balances storage and computing resources. However, SRAM-based computing-in-memory (CIM) architectures face challenges in delivering adequate on-chip storage while fulfilling computing requirements. To overcome this, we introduce a new MRAM-based near-memory computing (NMC) architecture. It retains the costeffective data access benefits of CIM while separating storage and computing at the macro-level, improving deployment adaptability. We refine the NMC macro by incorporating small temporary storage and adopting a layer-fusion approach to enhance data-transfer efficiency. By integrating a high-capacity MRAM into the macro, we attain a storage density of 0.532 um2/bit. Moreover, we enhance the adder tree with a shift module, supporting multiply-and-accumulate (MAC) operations at five distinct depths (8, 9, 16, 32, and 64), which raises resource utilization efficiency to 88.3%. Our architecture achieves an on-chip storage density of 1.49 Mb/mm2 and an energy efficiency of 6.164 TOPS/W.

Key words： INDEX TERMS Edge senarios; MRAM-based NMC macro; near-memory computing architecture

Cite this article

XI YANG , YAMIN MAO , LIANG CHANG , HAOJIE WEI , YUANBO WANG , JINGKE WANG , CHAO FAN , ZHONGMOU WU , SHOUZHONG PENG , JUN ZHOU . Edge-Optimized AI Architecture: MRAM-Based Near Memory Computing Macro Balancing Between Memory Capacity and Computation[J]. Integrated Circuits and Systems, 2025 , 2(1) : 4 -12 . DOI: 10.23919/ICS.2025.3553460

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