Integrated Circuits and Systems >
An Efficient Method for Analog Design Optimization With Layout Generators
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VEETI LAHTINEN (Student Member, IEEE), |
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ALEKSI TAMMINEN (Member, IEEE), |
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MARKO KOSUNEN (Member, IEEE) |
Received date: 2025-07-18
Revised date: 2025-09-03
Accepted date: 2025-09-19
Online published: 2025-12-24
Supported by
Aalto University School of Electrical Engineering
This paper describes an efficient fully programmatic and automated post-layout simulationbased optimization method for analog designs. The proposed methodology is developed to achieve the targeted performance objectives efficiently, that is, with reduced number of iterations and less simulation time, compared to currently predominantly manual design procedures. The efficiency of method is achieved through utilization of expert knowledge at every step of the proposed design process. The expert knowledge is supplied by formalizing the expression of design problems as nested functions, partitioning the design problem in both electrical and physical domains and by selection of starting point for the optimization. The circuit dependencies captured by the nested functions are augmented with backpropagation, similarly as in machinelearning. The proposed methodology provides a fully automated procedure for analog designs that incorporates extracted layout parasitic effects in all phases of the design process without human-in-the-loop. The effectiveness of the methodology is demonstrated with four example circuits: an inverter, a true single-phase clock flip-flop, a source follower, and a bootstrapped sampling switch. The variety of examples represent increasingly complex systems with increasing number of parameters, demonstrating capability of providing analog building blocks from specification to physical implementation without designer intervention.
SANTERI PORRASMAA , VEETI LAHTINEN , ALTTI HEIKKINEN , DHANASHREE BOOPATHY , ALEKSI TAMMINEN , MARKO KOSUNEN . An Efficient Method for Analog Design Optimization With Layout Generators[J]. Integrated Circuits and Systems, 2025 , 2(4) : 217 -232 . DOI: 10.23919/ICS.2025.3613289
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