A 64-Gb/s 0.33-pJ/Bit PAM4 Receiver Analog Front-End With a Single-Stage Triple-Peaking CTLE Achieving 22.5-dB Boost in 40-nm CMOS Process
GUOQING WANG, ZHAO ZHANG
Integrated Circuits and Systems . 2024, (2): 103 -108 .  DOI: 10.23919/ICS.2024.3456043