Special Issues and Sections

Wireline Communication and Heterogeneous Integration – Advances in Ultra-High-Speed Transceiver ICs

Call for Papers

Manuscript submission deadline: Jan. 15, 2025

 

The explosive growth of internet traffic and computing power drives the increasing demand for transceiver data rates. In recent years, the backbone of the internet and corporate networks, wireline communication has undergone significant transformations to accommodate the ever-growing throughput requirements of modern applications such as cloud computing, big data analytics, and ultra-high-definition multimedia streaming. This relentless push for higher data transmission rates has not only led to innovations in the realm of wireline technologies but also necessitated the integration of these systems with a variety of heterogeneous platforms ranging from advanced semiconductor materials to novel integration techniques involving photonic and electronic components.

 

The special issue aims to explore the coordination between wireline transceiver designs and heterogeneous integration techniques—a convergence that promises to enhance the performance, efficiency, and scalability of communication networks. Heterogeneous integration refers to the use of diverse components, often from different technological realms, integrated into a single system to leverage the unique advantages of each component. This approach can lead to significant improvements in speed, power efficiency, and functionality beyond what can be achieved with homogeneous systems. It covers the following topics and beyond:

 

· Energy-efficient and high-performance heterogeneous integration for communication systems;

· Advanced interface circuits for heterogeneous integration systems;

· High-performance transceivers for co-packaged optics (CPO);

· Analysis of signal integrity (SI) and power integrity (PI) in heterogeneous integrated systems;

· Innovations in single-ended and simultaneously bi-directional signaling for enhanced bandwidth density;

· Design methodologies for die-to-die and chiplet-based transceivers;

· High-performance clock and data recovery;

· Optical-electrical co-design and co-optimization strategies for advanced optical transceiver;

 

Submission procedure:


Prospective authors are invited to submit their papers following the instructions provided on the Integrated Circuits and Systems (ICAS) website: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=10410247. The submitted manuscripts should not have been previously published, nor should they be currently under consideration for publication elsewhere. The ICAS submission site: https://ieee.atyponrex.com/journal/ICAS.

 

Important dates:

Paper submission deadline: Jan. 15, 2025

First decision: Feb. 15, 2025

Revision submission:  Mar. 5, 2025, Final decision: Mar. 31, 2025

Final submission: April 10, 2025

 

Guest Editors:

Prof. Quan Pan, Southern University of Science and Technology

Prof. Nan Qi, Institute of Semiconductors, CAS

Prof. Cheng Wang, UESTC



Pubdate: 2024-10-10    Viewed: 305