Integrated Circuits and Systems >

2024 , Vol. 1 >Issue 3: 127 - 136

DOI: https://doi.org/10.23919/ICS.2024.3497916

Original article

A 100-mV-to-1.2-V Single-Ended Input Level Shifter for Wide-Range Voltage Conversion

  • CHAO WANG ,
  • YUXIN JI ,
  • JIAJIE HUANG ,
  • LIANG QI ,
  • YONGFU LI
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  • Department of Micro-Nano Electronics and MoE Key Lab of Artificial Intelligence, Shanghai Jiao Tong University, Shanghai 200240, China
+ CORRESPONDING AUTHOR: YONGFU LI(e-mail: ).

Received date: 2024-06-05

  Revised date: 2024-07-15

  Accepted date: 2024-09-18

  Online published: 2025-01-09

Supported by

the National Natural Science Foundation of China under Grant 62434006 and Grant(62350610271)

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Abstract

This brief presents an ultra-low voltage single-ended level shifter (LS) with a stacked current mirror and an improved split-controlled inverter as an output driver to enable wide-range voltage conversion. At the ultra-low input supply voltages, VDDL, the differential LS circuit will gradually be dysfunctional as the inverter produces limited voltage swings at the output. Some prior works have replaced the inverter with a pass transistor, whose gate is connected to the lower supply voltage, VDDL, to ensure the proper operation of the current mirror in its pull-up network (PUN). This requires the use of the “tie-high” standard cell to prevent gate breakdown in the pass transistor but it is unable to function properly at ultra-supply voltage. To solve this problem, we proposed to connect the pass transistor gate to the input transistor’s drain. The proposed LS circuit and prior single-ended LS circuit works have been fabricated in 55nm CMOS technology and a total of 10 chips for each circuit have been measured. The proposed LS circuit operates with a single input signal with a supply voltage of 100mV at a frequency of 1MHz. With a VDDL of 200mV and VDDH of 1.2V, the measured propagation delay is 182.1ns and the energy per transition (EPT) is around 4.35∼5.44 pJ. It has achieved a 1.08∼ 2.25× improvement in the Figure of Merit (FoM) than prior multi-supply works and a maximum improvement of 1134× compared to prior single-supply work. The FoM is based on the ratio between propagation delay and level conversion differences, which enables us to understand the circuit’s

ability to operate efficiently under wide signal-level conversion.

Key words： Current-mirror structure; level shifter; multi-supply voltage design; ultra-low-voltage interface.

Cite this article

CHAO WANG , YUXIN JI , JIAJIE HUANG , LIANG QI , YONGFU LI . A 100-mV-to-1.2-V Single-Ended Input Level Shifter for Wide-Range Voltage Conversion[J]. Integrated Circuits and Systems, 2024 , 1(3) : 127 -136 . DOI: 10.23919/ICS.2024.3497916

References

Publishing order | Descend order by publishing year | Descend order by cited within
[1].
L. Fassio et al., “A robust, high-speed and energy-efficient ultralow-voltage level shifter,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 68, no. 4, pp. 1393-1397, Apr. 2021.

[2].
D. Flynn et al., Low Power Methodology Manual: For System-on-Chip Design, 1st ed.ed. Berlin, Germany: Springer, 2010.

[3].
R. Lotfi, M. Saberi, S. R. Hosseini, A. R. Ahmadi-Mehr, and R. B. Staszewski, “Energy-efficient wide-range voltage level shifters reaching 4.2 fJ/Transition,” IEEE Solid-State Circuits Lett., vol. 1, no. 2, pp. 34-37, Feb. 2018.

[4].
M. Lanuzza, P. Corsonello, and S. Perri, “Fast and wide range voltage conversion in multisupply voltage designs,” IEEE Trans. Very Large Scale Integration Syst., vol. 23, no. 2, pp. 388-391, Feb. 2015.

[5].
A. Shapiro and E. G. Friedman, “Power efficient level shifter for 16 nm FinFET near threshold circuits,” IEEE Trans. Very Large Scale Integration Syst., vol. 24, no. 2, pp. 774-778, Feb. 2016.

[6].
S. R. Hosseini, M. Saberi, and R. Lotfi, “A high-speed and power-efficient voltage level shifter for dual-supply applications,” IEEE Trans. Very Large Scale Integration Syst., vol. 25, no. 3, pp. 1154-1158, Mar. 2017.

[7].
T.-H. Chen, J. Chen, and L. T. Clark, “Subthreshold to above threshold level shifter design,” J. Low Power Electron., vol. 2, no. 2, pp. 251-258, Aug. 2006.

[8].
S. Lütkemeier and U. Rückert, “A subthreshold to above-threshold level shifter comprising a wilson current mirror,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 9, pp. 721-724, Sep. 2010.

[9].
M. Lanuzza, P. Corsonello, and S. Perri, “Low-power level shifter for multi-supply voltage designs,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 59, no. 12, pp. 922-926, Dec. 2012.

[10].
S. R. Hosseini, M. Saberi, and R. Lotfi, “A low-power subthreshold to above-threshold voltage level shifter,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 61, no. 10, pp. 753-757, Oct. 2014.

[11].
J. Zhou et al., “An ultra-low voltage level shifter using revised wilson current mirror for fast and energy-efficient wide-range voltage conversion from sub-threshold to I/O voltage,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 3, pp. 697-706, Mar. 2015.

[12].
R. Matsuzuka, T. Hirose, Y. Shizuku, N. Kuroki, and M. Numa, “A 0.19-V minimum input low energy level shifter for extremely low-voltage VLSIs,” in Proc. IEEE Int. Symp. Circuits Syst., May 2015, pp. 2948-2951.

[13].
N. Cuevas and E. Roa, “An all low-voltage devices level shifter with stress protection for powering events,” in Proc. IEEE Int. Symp. Circuits Syst., Oct. 2020, pp. 1-4.

[14].
V. L. Le and T. T. H. Kim, “An area and energy efficient ultra-low voltage level shifter with pass transistor and reduced-swing output buffer in 65-Nm CMOS,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 65, no. 5, pp. 607-611, May 2018.

[15].
S. Kabirpour and M. Jalali, “A power-delay and area efficient voltage level shifter based on a reflected-output wilson current mirror level shifter,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 67, no. 2, pp. 250-254, Feb. 2020.

[16].
C. Huang and H. Jiao, “C3MLS: An ultra-wide-range energy-efficient level shifter with CCLS/CMLS hybrid structure,” IEEE J. Solid-State Circuits, vol. 58, no. 10, pp. 2685-2695, Oct. 2023.

[17].
A. A. Vatanjou, T. Ytterdal, and S. Aunet, “An ultra-low voltage and low-energy level shifter in 28-Nm UTBB-FDSOI,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 66, no. 6, pp. 899-903, Jun. 2019. Y. Ho, S. Y. Hsu, and C. Y. Lee, “A variation-tolerant subthreshold to superthreshold level shifter for heterogeneous interfaces,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 63, no. 2, pp. 161-165, Feb. 2016.

[18].
Y. Osaki, T. Hirose, N. Kuroki, and M. Numa, “A low-power level shifter with logic error correction for extremely low-voltage digital CMOS LSIs,” IEEE J. Solid-State Circuits, vol. 47, no. 7, pp. 1776-1783, Jul. 2012.

[19].
Y. Moghe, T. Lehmann, and T. Piessens, “Nanosecond delay floating high voltage level shifters in a 0.35µHV-CMOS technology,” IEEE J. Solid-State Circuits, vol. 46, no. 2, pp. 485-497, Feb. 2011.

[20].
W. Zhao, A. B. Alvarez, and Y. Ha, “A 65-nm 25.1-ns 30.7-fJ robust subthreshold level shifter with wide conversion range,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 62, no. 7, pp. 671-675, Jul. 2015.

[21].
B. Mohammadi and J. N. Rodrigues,“A 65 nm single stage 28 fJ/Cycle 0.12 to 1.2 V level-shifter,” in Proc. 2014 IEEE Int. Symp. Circuits Syst., Jun. 2014, pp.990-993.

[22].
S. C. Luo, C. J. Huang, and Y. H. Chu, “A wide-range level shifter using a modified wilson current mirror hybrid buffer,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 6, pp. 1656-1665, Jun. 2014.

[23].
L. Wen, X. Cheng, S. Tian, H. Wen, and X. Zeng, “Subthreshold level shifter with self-controlled current limiter by detecting output error,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 63, no. 4, pp. 346-350, Apr. 2016.

[24].
E. Maghsoudloo, M. Rezaei, M. Sawan, and B. Gosselin, “A high-speed and ultra low-power subthreshold signal level shifter,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 64, no. 5, pp. 1164-1172, May 2017.

[25].
Y. Cao, B. Wang, X. Pan, X. Zhao, Z. Wen, and A. Bermak, “A compact 31.47 fJ/Conversion subthreshold level shifter with wide conversion range in 65 nm MTCMOS,” IEEE Access, vol. 6, pp. 54976-54981, 2018.

[26].
X. Chen, T. Zhou, J. Huang, G. Wang, and Y. Li, “A sub-100 mV ultra-low voltage level-shifter using current limiting cross-coupled technique for wide-range conversion to I/O voltage,” IEEE Access, vol. 8, pp. 145577-145585, 2020.

[27].
M. Karimi et al., “A 7.6-ns delay subthreshold level-shifter leveraging a composite transistor and a voltage-controlled current source,” IEEE Access, vol. 10, pp. 132432-132447, 2022.

[28].
J. Park and H. Jeong, “Energy-efficient wide-range level shifter with a logic error detection circuit,” IEEE Trans. Very Large Scale Integration Syst., vol. 31, no. 5, pp. 701-705, May 2023.

[29].
C. Wang, Y. Ji, C. Ma, Q. Cai, L. Qi, and Y. Li, “An ultra-low-voltage level shifter with embedded re-configurable logic and time-borrowing latch technique,” IEEE Access, vol. 9, pp. 79904-79910, 2021.

[30].
H. Jeong, T.-H. Kim, C. N. Park, H. Kim, T. Song, and S.-O. Jung, “A wide-range static current-free current mirror-based LS with logic error detection for near-threshold operation,” IEEE J. Solid-State Circuits, vol. 56, no. 2, pp. 554-565, Feb. 2021.

[31].
H. You, J. Yuan, W. Tang, S. Qiao, and Y. Hei, “An energy-efficient level shifter for ultra low-voltage digital LSIs,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 67, no. 12, pp. 3357-3361, Dec. 2020.

[32].
M. N. Sharafi, H. Rashidian, and N. Shiri, “A 38.5-fJ 14.4-ns robust and efficient subthreshold-to-suprathreshold voltage-level shifter comprising logic mismatch-activated current control circuit,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 70, no. 6, pp. 1906-1910, Jun. 2023.

[33].
Z. Yong, X. Xiang, C. Chen, and J. Meng, “An energy-efficient and wide-range voltage level shifter with dual current mirror,” IEEE Trans. Very Large Scale Integration Syst., vol. 25, no. 12, pp. 3534-3538, Dec. 2017.

[34].
R. Matsuzuka, T. Hirose, Y. Shizuku, K. Shinonaga, N. Kuroki, and M. Numa, “An 80-mV-to-1.8-V conversion-range low-energy level shifter for extremely low-voltage VLSIs,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 64, no. 8, pp. 2026-2035, Aug. 2017.

[35].
P. Shukla, P. Singh, T. Maheshwari, A. Grover, and V. Rana, “A 800 MHz, 0.21pJ, 1.2 V to 6 V level shifter using thin gate oxide devices in 65 nm LSTP,” in Proc. 27th IEEE Int. Conf. Electron., Circuits Syst., Nov. 2020, pp. 1-4.

[36].
M. Lanuzza, F. Crupi, S. Rao, R. De Rose, S. Strangio, and G. Iannac- cone, “An ultralow-voltage energy-efficient level shifter,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 64, no. 1, pp. 61-65, Jan. 2017.

[37].
S. S. Kabirpour and M. Jalali, “A low-power and high-speed voltage level shifter based on a regulated cross-coupled pull-up network,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 66, no. 6, pp. 909-913, Jun. 2019.

[38].
E. Låte, T. Ytterdal, and S. Aunet, “An energy efficient level shifter capable of logic conversion from sub-15 mV to 1.2 V,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 67, no. 11, pp. 2687-2691, Nov. 2020.

[39].
C. Wang et al., “An ultra low voltage energy efficient level shifter with current limiter and improved split-controlled inverter,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 71, no. 5, pp. 2569-2573, May 2024.

[40].
A. Yuan, H. Zhao, X. Wang, Z. Li, and S. Qiao, “An ultra-low leakage and wide-range voltage level shifter for low-power digital CMOS VLSIs,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 71, no. 3, pp. 1406-1410, Mar. 2024.

[41].
Y. Li, J. Zhao, Y. Liu, and G. Wang, “A comprehensive study on the design methodology of level shifter circuits,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 70, no. 1, pp. 302-314, Jan. 2023.

[42].
M. Declerq, M. Schubert, and F. Clement, “5 V-to-75 V. CMOS output interface circuits,” in Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1993, pp. 162-163.

[43].
R. Puri et al., “Pushing ASIC performance in a power envelope,” in Proc. Des. Automat. Conf., Jun. 2003, pp. 788-793.

[44].
J. C. García et al., “High performance single supply CMOS inverter level up shifter for multi-supply voltages domains,” in Proc. Des., Automat. Test Europe Conf., Mar. 2015, pp. 1273-1276.

[45].
S. Fang and E. Salman, “Low swing TSV signaling using novel level shifters with single supply voltage,” in Proc. IEEE Int. Symp. Circuits Syst., May 2015, pp. 1965-1968.

[46].
J. C. García, A. Juan, and S. Nooshabadi, “Single supply CMOS up level shifter for dual voltage system,” in Proc. IEEE Int. Symp. Circuits Syst., May 2017, pp. 1-4.

[47].
D. S. Truesdell and B. H. Calhoun,“A single-supply 6-transistor voltage level converter design reaching 8.18-fj/transition at 0.3-1.2-V RANGE or 44-fW leakage at 0.8-2. 5-V range,” IEEE Solid-State Circuits Lett., vol. 3, pp. 502-505, 2020.

[48].
Q. Khan, S. Wadhwa, and K. Misri, “A single supply level shifter for multi-voltage systems,” in Proc. Int. Conf. VLSI Des., Jan. 2006, pp. 1-4.

[49].
R. Garg, G. Mallarapu, and S. P. Khatri, “A single-supply true voltage level shifter,” in Proc. Des., Automat. Test Europe Conf., Mar. 2008, pp. 979-984.

[50].
M. S. Hossain and I. Savidis, “Bi-directional input/output circuits with integrated level shifters for near-threshold computing,” in Proc. IEEE Int. Midwest Symp. Circuits Syst., Aug. 2017, pp. 1240-1243.

[51].
M. Karimi et al., “A 1.99-ns 0.5-pJ wide frequency range level shifter with closed-loop negative feedback,” in Proc. IEEE Int. New Circuits Syst. Conf., Jun. 2020, pp. 174-177.

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