Integrated Circuits and Systems >

2025 , Vol. 2 >Issue 4: 205 - 216

DOI: https://doi.org/10.23919/ICS.2025.3565481

Regular Papers

HDD-RAM: A 40-nm 0.35 V 25 MHz Half-Select Disturb-Free Memory With Data-Aware 10T SRAM

  • YIFEI LI 1 ,
  • JIAN CHEN 1 ,
  • YUQI WANG 2 ,
  • WENFENG ZHAO 3 ,
  • YUHAO SHU , 4 ,
  • YAJUN HA , 1, 5
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  • 1 School of Information Science and Technology, ShanghaiTech University, Shanghai 201210
  • 2 China Swiss Federal Institute of Technology in Lausanne (EPFL), 1015 Lausanne, Switzerland
  • 3 Department of Electrical and Computer Engineering, Binghamton University, State University of New York (SUNY), Binghamton, NY 13902
  • 4 USA College of Integrated Circuits, Nanjing University of Aeronautics and Astronautics, Nanjing 210016, China
  • 5 Shanghai Engineering Research Center of Energy Efficient and Custom AI IC, Shanghai 200062, China
YUHAO SHU (e-mail: );
YAJUN HA (e-mail: ).

YIFEI LI (Graduate Student Member, IEEE),

YUQI WANG (Graduate Student Member, IEEE),

WENFENG ZHAO (Member, IEEE),

YUHAO SHU (Member, IEEE),

YAJUN HA (Senior Member, IEEE)

Received date: 2025-03-18

  Revised date: 2025-04-19

  Accepted date: 2025-04-22

  Online published: 2025-12-24

Supported by

National Natural Science Foundation of China(62150710549)

National Natural Science Foundation of China(U2441247)

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Abstract

Ultra-low-voltage SRAM is an indispensable component that is increasingly adopted in energyefficient computing systems. However, it comes at the cost of increased sensitivity to soft errors. To address this issue, bit-interleaving SRAM is widely used to mitigate soft errors. But it suffers from half-select disturbance. Previous works address such disturbance by using a dedicated write port or enhanced write assist scheme. However, these works may decrease write margin, induce high cell-level write latency, or incur architecture-level time/timing overhead. In this paper, we develop a high-speed bit-interleaving half-select disturb-free memory with data-aware 10T SRAM. First, we present an isolated and decoupled topology with dedicated write control to improve stability. Second, we present a data-aware write path with enhanced write-ability that effectively reduces the write access time. A 40-nm 4-Kb test chip has been fabricated to validate the optimizations above. Measurement results show that our half-select disturb-free test chip achieves a peak operating frequency of 25 MHz and an energy consumption of 0.168 fJ/bit with a supply voltage of 0.35 V. Compared with the state-of-the-art designs, it has achieved a speed up of 2.72× and an energy saving of 93.8%.

Key words： Ultra-low-voltage; SRAM; soft error; bit-interleaving; half-select; disturb-free

Cite this article

YIFEI LI , JIAN CHEN , YUQI WANG , WENFENG ZHAO , YUHAO SHU , YAJUN HA . HDD-RAM: A 40-nm 0.35 V 25 MHz Half-Select Disturb-Free Memory With Data-Aware 10T SRAM[J]. Integrated Circuits and Systems, 2025 , 2(4) : 205 -216 . DOI: 10.23919/ICS.2025.3565481

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